mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 12:26:41 +07:00
iwlwifi: remove legacy isr tasklet
After driver split, no need for support legacy isr, remove it. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
This commit is contained in:
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4263108c2a
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d6b8061824
@ -59,8 +59,6 @@ void iwl_free_isr_ict(struct iwl_priv *priv)
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int iwl_alloc_isr_ict(struct iwl_priv *priv)
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{
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if (priv->cfg->base_params->use_isr_legacy)
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return 0;
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/* allocate shrared data table */
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priv->_agn.ict_tbl_vir =
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dma_alloc_coherent(&priv->pci_dev->dev,
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@ -652,8 +652,7 @@ int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
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if (!priv->cfg->base_params->use_isr_legacy)
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rb_timeout = RX_RB_TIMEOUT;
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rb_timeout = RX_RB_TIMEOUT;
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if (priv->cfg->mod_params->amsdu_size_8K)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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@ -845,191 +845,6 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv)
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tasklet_kill(&priv->irq_tasklet);
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}
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static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
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{
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u32 inta, handled = 0;
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u32 inta_fh;
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unsigned long flags;
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u32 i;
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#ifdef CONFIG_IWLWIFI_DEBUG
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u32 inta_mask;
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#endif
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spin_lock_irqsave(&priv->lock, flags);
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/* Ack/clear/reset pending uCode interrupts.
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* Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
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* and will clear only when CSR_FH_INT_STATUS gets cleared. */
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inta = iwl_read32(priv, CSR_INT);
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iwl_write32(priv, CSR_INT, inta);
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/* Ack/clear/reset pending flow-handler (DMA) interrupts.
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* Any new interrupts that happen after this, either while we're
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* in this tasklet, or later, will show up in next ISR/tasklet. */
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inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
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iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
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/* just for debug */
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inta_mask = iwl_read32(priv, CSR_INT_MASK);
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IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
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inta, inta_mask, inta_fh);
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}
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#endif
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
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* atomic, make sure that inta covers all the interrupts that
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* we've discovered, even if FH interrupt came in just after
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* reading CSR_INT. */
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if (inta_fh & CSR49_FH_INT_RX_MASK)
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inta |= CSR_INT_BIT_FH_RX;
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if (inta_fh & CSR49_FH_INT_TX_MASK)
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inta |= CSR_INT_BIT_FH_TX;
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/* Now service all interrupt bits discovered above. */
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if (inta & CSR_INT_BIT_HW_ERR) {
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IWL_ERR(priv, "Hardware error detected. Restarting.\n");
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/* Tell the device to stop sending interrupts */
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iwl_disable_interrupts(priv);
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priv->isr_stats.hw++;
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iwl_irq_handle_error(priv);
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handled |= CSR_INT_BIT_HW_ERR;
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return;
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}
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
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/* NIC fires this, but we don't use it, redundant with WAKEUP */
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if (inta & CSR_INT_BIT_SCD) {
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IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
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"the frame/frames.\n");
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priv->isr_stats.sch++;
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}
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/* Alive notification via Rx interrupt will do the real work */
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if (inta & CSR_INT_BIT_ALIVE) {
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IWL_DEBUG_ISR(priv, "Alive interrupt\n");
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priv->isr_stats.alive++;
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}
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}
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#endif
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/* Safely ignore these bits for debug checks below */
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inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
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/* HW RF KILL switch toggled */
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if (inta & CSR_INT_BIT_RF_KILL) {
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int hw_rf_kill = 0;
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if (!(iwl_read32(priv, CSR_GP_CNTRL) &
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CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
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hw_rf_kill = 1;
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IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
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hw_rf_kill ? "disable radio" : "enable radio");
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priv->isr_stats.rfkill++;
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/* driver only loads ucode once setting the interface up.
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* the driver allows loading the ucode even if the radio
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* is killed. Hence update the killswitch state here. The
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* rfkill handler will care about restarting if needed.
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*/
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if (!test_bit(STATUS_ALIVE, &priv->status)) {
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if (hw_rf_kill)
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set_bit(STATUS_RF_KILL_HW, &priv->status);
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else
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clear_bit(STATUS_RF_KILL_HW, &priv->status);
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wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
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}
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handled |= CSR_INT_BIT_RF_KILL;
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}
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/* Chip got too hot and stopped itself */
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if (inta & CSR_INT_BIT_CT_KILL) {
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IWL_ERR(priv, "Microcode CT kill error detected.\n");
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priv->isr_stats.ctkill++;
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handled |= CSR_INT_BIT_CT_KILL;
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}
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/* Error detected by uCode */
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if (inta & CSR_INT_BIT_SW_ERR) {
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IWL_ERR(priv, "Microcode SW error detected. "
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" Restarting 0x%X.\n", inta);
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priv->isr_stats.sw++;
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iwl_irq_handle_error(priv);
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handled |= CSR_INT_BIT_SW_ERR;
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}
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/*
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* uCode wakes up after power-down sleep.
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* Tell device about any new tx or host commands enqueued,
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* and about any Rx buffers made available while asleep.
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*/
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if (inta & CSR_INT_BIT_WAKEUP) {
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IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
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iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
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for (i = 0; i < priv->hw_params.max_txq_num; i++)
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iwl_txq_update_write_ptr(priv, &priv->txq[i]);
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priv->isr_stats.wakeup++;
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handled |= CSR_INT_BIT_WAKEUP;
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}
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/* All uCode command responses, including Tx command responses,
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* Rx "responses" (frame-received notification), and other
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* notifications from uCode come through here*/
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if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
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iwl_rx_handle(priv);
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priv->isr_stats.rx++;
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handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
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}
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/* This "Tx" DMA channel is used only for loading uCode */
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if (inta & CSR_INT_BIT_FH_TX) {
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IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
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priv->isr_stats.tx++;
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handled |= CSR_INT_BIT_FH_TX;
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/* Wake up uCode load routine, now that load is complete */
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priv->ucode_write_complete = 1;
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wake_up_interruptible(&priv->wait_command_queue);
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}
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if (inta & ~handled) {
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IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
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priv->isr_stats.unhandled++;
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}
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if (inta & ~(priv->inta_mask)) {
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IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
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inta & ~priv->inta_mask);
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IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
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}
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/* Re-enable all interrupts */
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/* only Re-enable if disabled by irq */
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if (test_bit(STATUS_INT_ENABLED, &priv->status))
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iwl_enable_interrupts(priv);
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/* Re-enable RF_KILL if it occurred */
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else if (handled & CSR_INT_BIT_RF_KILL)
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iwl_enable_rfkill_int(priv);
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
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inta = iwl_read32(priv, CSR_INT);
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inta_mask = iwl_read32(priv, CSR_INT_MASK);
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inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
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IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
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"flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
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}
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#endif
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}
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/* tasklet for iwlagn interrupt */
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static void iwl_irq_tasklet(struct iwl_priv *priv)
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{
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@ -3751,12 +3566,8 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
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priv->watchdog.data = (unsigned long)priv;
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priv->watchdog.function = iwl_bg_watchdog;
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if (!priv->cfg->base_params->use_isr_legacy)
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tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
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iwl_irq_tasklet, (unsigned long)priv);
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else
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tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
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iwl_irq_tasklet_legacy, (unsigned long)priv);
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tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
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iwl_irq_tasklet, (unsigned long)priv);
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}
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static void iwl_cancel_deferred_work(struct iwl_priv *priv)
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@ -291,7 +291,6 @@ struct iwl_base_params {
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bool set_l0s;
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bool use_bsm;
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bool use_isr_legacy;
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const u16 max_ll_items;
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const bool shadow_ram_support;
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u16 led_compensation;
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