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drm/amd/display: Display goes blank after inst

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[why]
Display goes blank after driver installation.
Aux tuning parameters must be used for 2.x only.
Wrong dc_golden_table offset was used.

[How]
Implement a new enc3_hw_init function without VBIOS constants usage to
be called for 3.x
Calculate dc_golden_table offset using sum of
base dce_info offset and golden table offset

Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Igor Kravchenko 2020-07-24 11:10:40 -04:00 committed by Alex Deucher
parent ab2cf4c86b
commit d6a4e5e9fe
3 changed files with 56 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -2101,7 +2101,7 @@ static struct atom_dc_golden_table_v1 *bios_get_golden_table(
DATA_TABLES(dce_info));
if (!disp_cntl_tbl_4_4)
return NULL;
dc_golden_offset = disp_cntl_tbl_4_4->dc_golden_table_offset;
dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
*dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
break;
}
@ -2115,7 +2115,7 @@ static struct atom_dc_golden_table_v1 *bios_get_golden_table(
return NULL;
return GET_IMAGE(struct atom_dc_golden_table_v1,
dc_golden_offset);
dc_golden_offset);
}
static enum bp_result bios_get_atom_dc_golden_table(

53
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c
View File

@ -62,7 +62,7 @@ static const struct link_encoder_funcs dcn30_link_enc_funcs = {
.read_state = link_enc2_read_state,
.validate_output_with_stream =
dcn30_link_encoder_validate_output_with_stream,
.hw_init = enc2_hw_init,
.hw_init = enc3_hw_init,
.setup = dcn10_link_encoder_setup,
.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
.enable_dp_output = dcn20_link_encoder_enable_dp_output,
@ -203,3 +203,54 @@ void dcn30_link_encoder_construct(
enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
}
}
#define AUX_REG(reg)\
(enc10->aux_regs->reg)
#define AUX_REG_READ(reg_name) \
dm_read_reg(CTX, AUX_REG(reg_name))
#define AUX_REG_WRITE(reg_name, val) \
dm_write_reg(CTX, AUX_REG(reg_name), val)
void enc3_hw_init(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
/*
00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
*/
/*
AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
AUX_RX_START_WINDOW = 1 [6:4]
AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
AUX_RX_DETECTION_THRESHOLD [30:28] = 1
*/
AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
// 27MHz -> 0xd
// 100MHz -> 0x32
// 48MHz -> 0x18
// Set TMDS_CTL0 to 1. This is a legacy setting.
REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
dcn10_aux_initialize(enc10);
}

2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h
View File

@ -73,4 +73,6 @@ void dcn30_link_encoder_construct(
const struct dcn10_link_enc_shift *link_shift,
const struct dcn10_link_enc_mask *link_mask);
void enc3_hw_init(struct link_encoder *enc);
#endif /* __DC_LINK_ENCODER__DCN30_H__ */