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drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1166,7 +1166,7 @@ static int sdma_v5_2_sw_init(void *handle)
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return r;
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/* SDMA trap event */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3,
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid,
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SDMA3_5_0__SRCID__SDMA_TRAP,
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&adev->sdma.trap_irq);
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if (r)
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@ -1408,7 +1408,7 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
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break;
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}
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break;
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case SOC15_IH_CLIENTID_SDMA3:
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case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
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switch (entry->ring_id) {
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case 0:
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amdgpu_fence_process(&adev->sdma.instance[3].ring);
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@ -66,6 +66,7 @@ enum soc15_ih_clientid {
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SOC15_IH_CLIENTID_VCN1 = SOC15_IH_CLIENTID_UVD1,
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SOC15_IH_CLIENTID_SDMA2 = SOC15_IH_CLIENTID_ACP,
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SOC15_IH_CLIENTID_SDMA3 = SOC15_IH_CLIENTID_DCE,
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SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = SOC15_IH_CLIENTID_ISP,
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SOC15_IH_CLIENTID_SDMA4 = SOC15_IH_CLIENTID_ISP,
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SOC15_IH_CLIENTID_SDMA5 = SOC15_IH_CLIENTID_VCE0,
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SOC15_IH_CLIENTID_SDMA6 = SOC15_IH_CLIENTID_XDMA,
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