AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-02-21 02:57:32 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

net: ipa: share field mask values for GSI global interrupt

Browse Source 
The GSI global interrupt is managed by three registers: enable;
status; and clear.  The three registers have same set of field bits
at the same locations.  Use a common set of field masks for all
three registers to avoid duplication.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder 2020-09-28 18:04:42 -05:00 committed by David S. Miller
parent e6580d0eb7
commit d61bb7166d
2 changed files with 8 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/ipa/gsi.c
View File

@ -1074,8 +1074,8 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
val &= ~ERROR_INT_FMASK;
if (val & EN_GP_INT1_FMASK) {
val ^= EN_GP_INT1_FMASK;
if (val & GP_INT1_FMASK) {
val ^= GP_INT1_FMASK;
gsi_isr_gp_int1(gsi);
}

21
drivers/net/ipa/gsi_reg.h
View File

@ -321,29 +321,20 @@
GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
(0x0001f100 + 0x4000 * (ee))
#define ERROR_INT_FMASK GENMASK(0, 0)
#define GP_INT1_FMASK GENMASK(1, 1)
#define GP_INT2_FMASK GENMASK(2, 2)
#define GP_INT3_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
(0x0001f108 + 0x4000 * (ee))
#define EN_ERROR_INT_FMASK GENMASK(0, 0)
#define EN_GP_INT1_FMASK GENMASK(1, 1)
#define EN_GP_INT2_FMASK GENMASK(2, 2)
#define EN_GP_INT3_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0)
#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
(0x0001f110 + 0x4000 * (ee))
#define CLR_ERROR_INT_FMASK GENMASK(0, 0)
#define CLR_GP_INT1_FMASK GENMASK(1, 1)
#define CLR_GP_INT2_FMASK GENMASK(2, 2)
#define CLR_GP_INT3_FMASK GENMASK(3, 3)
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define ERROR_INT_FMASK GENMASK(0, 0)
#define GP_INT1_FMASK GENMASK(1, 1)
#define GP_INT2_FMASK GENMASK(2, 2)
#define GP_INT3_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0)
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)