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ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE, thus the DI0 interface will be turned off inadvertently during boot. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -514,7 +514,7 @@ static void __init mx53_clocks_init(struct device_node *np)
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clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
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clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
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mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
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clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
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clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
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clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
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clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
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mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
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