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drm/i915: Ensure all PLL registers are flushed before a udelay()

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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-09-10 22:33:19 +01:00
parent c64e311e65
commit d5e0d2f519
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/i915/intel_display.c
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@ -1641,6 +1641,7 @@ static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
dpa_ctl |= DP_PLL_FREQ_270MHZ; dpa_ctl |= DP_PLL_FREQ_270MHZ;
} }
I915_WRITE(DP_A, dpa_ctl); I915_WRITE(DP_A, dpa_ctl);
POSTING_READ(DP_A);
udelay(500); udelay(500);
} }
@ -1708,6 +1709,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
temp &= ~FDI_LINK_TRAIN_NONE; temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2; temp |= FDI_LINK_TRAIN_PATTERN_2;
I915_WRITE(fdi_rx_reg, temp); I915_WRITE(fdi_rx_reg, temp);
POSTING_READ(fdi_rx_reg);
udelay(150); udelay(150);
tries = 0; tries = 0;
@ -1788,6 +1790,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
temp |= snb_b_fdi_train_param[i]; temp |= snb_b_fdi_train_param[i];
I915_WRITE(fdi_tx_reg, temp); I915_WRITE(fdi_tx_reg, temp);
POSTING_READ(fdi_tx_reg);
udelay(500); udelay(500);
temp = I915_READ(fdi_rx_iir_reg); temp = I915_READ(fdi_rx_iir_reg);
@ -1823,6 +1826,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp |= FDI_LINK_TRAIN_PATTERN_2; temp |= FDI_LINK_TRAIN_PATTERN_2;
} }
I915_WRITE(fdi_rx_reg, temp); I915_WRITE(fdi_rx_reg, temp);
POSTING_READ(fdi_rx_reg);
udelay(150); udelay(150);
for (i = 0; i < 4; i++ ) { for (i = 0; i < 4; i++ ) {
@ -1830,6 +1834,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
temp |= snb_b_fdi_train_param[i]; temp |= snb_b_fdi_train_param[i];
I915_WRITE(fdi_tx_reg, temp); I915_WRITE(fdi_tx_reg, temp);
POSTING_READ(fdi_tx_reg);
udelay(500); udelay(500);
temp = I915_READ(fdi_rx_iir_reg); temp = I915_READ(fdi_rx_iir_reg);