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drm/amd/display: fix underflow on boot

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[Why]
New seamless boot sequence introduced a bug where front end is disabled
without blanking otg.

[How]
Adjust the condition of blanking otg to match seamless boot.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang 2019-03-25 16:11:43 -04:00 committed by Alex Deucher
parent 15ae3b28f8
commit d5ca5fdbeb
1 changed files with 2 additions and 4 deletions
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6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
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@ -979,16 +979,14 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
* to non-preferred front end. If pipe_ctx->stream is not NULL,
* we will use the pipe, so don't disable
*/
if (pipe_ctx->stream != NULL)
if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
continue;
if (tg->funcs->is_tg_enabled(tg))
tg->funcs->lock(tg);
/* Blank controller using driver code instead of
* command table.
*/
if (tg->funcs->is_tg_enabled(tg)) {
tg->funcs->lock(tg);
tg->funcs->set_blank(tg, true);
hwss_wait_for_blank_complete(tg);
}