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dt-bindings: net: meson-dwmac: convert to yaml
Now that we have the DT validation in place, let's convert the device tree bindings for the Synopsys DWMAC Glue for Amlogic SoCs over to a YAML schemas. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Neil Armstrong
David S. Miller
parent
57b77df7b7
commit
d5a57e4e31
113
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
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113
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
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@ -0,0 +1,113 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson DWMAC Ethernet controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,meson6-dwmac
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- amlogic,meson8b-dwmac
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- amlogic,meson8m2-dwmac
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- amlogic,meson-gxbb-dwmac
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- amlogic,meson-axg-dwmac
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required:
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- compatible
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allOf:
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- $ref: "snps,dwmac.yaml#"
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- if:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,meson8b-dwmac
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- amlogic,meson8m2-dwmac
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- amlogic,meson-gxbb-dwmac
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- amlogic,meson-axg-dwmac
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then:
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properties:
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clocks:
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items:
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- description: GMAC main clock
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- description: First parent clock of the internal mux
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- description: Second parent clock of the internal mux
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clock-names:
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minItems: 3
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maxItems: 3
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items:
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- const: stmmaceth
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- const: clkin0
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- const: clkin1
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amlogic,tx-delay-ns:
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$ref: /schemas/types.yaml#definitions/uint32
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description:
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The internal RGMII TX clock delay (provided by this driver) in
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nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
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When phy-mode is set to "rgmii" then the TX delay should be
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explicitly configured. When not configured a fallback of 2ns is
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used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
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the TX clock delay is already provided by the PHY. In that case
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this property should be set to 0ns (which disables the TX clock
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delay in the MAC to prevent the clock from going off because both
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PHY and MAC are adding a delay).
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Any configuration is ignored when the phy-mode is set to "rmii".
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properties:
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compatible:
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additionalItems: true
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maxItems: 3
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items:
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- enum:
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- amlogic,meson6-dwmac
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- amlogic,meson8b-dwmac
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- amlogic,meson8m2-dwmac
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- amlogic,meson-gxbb-dwmac
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- amlogic,meson-axg-dwmac
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contains:
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enum:
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- snps,dwmac-3.70a
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- snps,dwmac
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reg:
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items:
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- description:
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The first register range should be the one of the DWMAC controller
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- description:
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The second range is is for the Amlogic specific configuration
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(for example the PRG_ETHERNET register range on Meson8b and newer)
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- phy-mode
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examples:
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- |
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ethmac: ethernet@c9410000 {
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compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
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reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
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interrupts = <8>;
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interrupt-names = "macirq";
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clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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phy-mode = "rgmii";
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};
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@ -1,71 +0,0 @@
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* Amlogic Meson DWMAC Ethernet controller
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The device inherits all the properties of the dwmac/stmmac devices
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described in the file stmmac.txt in the current directory with the
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following changes.
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Required properties on all platforms:
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- compatible: Depending on the platform this should be one of:
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- "amlogic,meson6-dwmac"
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- "amlogic,meson8b-dwmac"
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- "amlogic,meson8m2-dwmac"
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- "amlogic,meson-gxbb-dwmac"
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- "amlogic,meson-axg-dwmac"
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Additionally "snps,dwmac" and any applicable more
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detailed version number described in net/stmmac.txt
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should be used.
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- reg: The first register range should be the one of the DWMAC
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controller. The second range is is for the Amlogic specific
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configuration (for example the PRG_ETHERNET register range
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on Meson8b and newer)
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Required properties on Meson8b, Meson8m2, GXBB and newer:
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- clock-names: Should contain the following:
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- "stmmaceth" - see stmmac.txt
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- "clkin0" - first parent clock of the internal mux
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- "clkin1" - second parent clock of the internal mux
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Optional properties on Meson8b, Meson8m2, GXBB and newer:
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- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
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by this driver) in nanoseconds. Allowed values
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are: 0ns, 2ns, 4ns, 6ns.
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When phy-mode is set to "rgmii" then the TX
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delay should be explicitly configured. When
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not configured a fallback of 2ns is used.
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When the phy-mode is set to either "rgmii-id"
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or "rgmii-txid" the TX clock delay is already
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provided by the PHY. In that case this
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property should be set to 0ns (which disables
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the TX clock delay in the MAC to prevent the
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clock from going off because both PHY and MAC
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are adding a delay).
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Any configuration is ignored when the phy-mode
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is set to "rmii".
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Example for Meson6:
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ethmac: ethernet@c9410000 {
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compatible = "amlogic,meson6-dwmac", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108108 0x4>;
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interrupts = <0 8 1>;
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interrupt-names = "macirq";
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clocks = <&clk81>;
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clock-names = "stmmaceth";
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}
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Example for GXBB:
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ethmac: ethernet@c9410000 {
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compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
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reg = <0x0 0xc9410000 0x0 0x10000>,
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<0x0 0xc8834540 0x0 0x8>;
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interrupts = <0 8 1>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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phy-mode = "rgmii";
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};
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@ -50,6 +50,11 @@ properties:
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- allwinner,sun8i-r40-emac
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- allwinner,sun8i-v3s-emac
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- allwinner,sun50i-a64-emac
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- amlogic,meson6-dwmac
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- amlogic,meson8b-dwmac
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- amlogic,meson8m2-dwmac
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- amlogic,meson-gxbb-dwmac
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- amlogic,meson-axg-dwmac
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- snps,dwmac
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- snps,dwmac-3.50a
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- snps,dwmac-3.610
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