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ARM: OMAP3: clock: remove un-used core dpll re-program code
Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo
Tony Lindgren
parent
ae428a72b4
commit
d42f265a5d
@ -48,11 +48,9 @@ AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
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# Functions loaded to SRAM
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obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
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obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
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obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
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AFLAGS_sram242x.o :=-Wa,-march=armv6
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AFLAGS_sram243x.o :=-Wa,-march=armv6
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AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
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# Restart code (OMAP4/5 currently in omap4-common.c)
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obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
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@ -186,7 +184,6 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
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@ -1,122 +0,0 @@
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/*
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* OMAP34xx M2 divider clock code
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock3xxx.h"
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#include "sdrc.h"
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#include "sram.h"
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#define CYCLES_PER_MHZ 1000000
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struct clk *sdrc_ick_p, *arm_fck_p;
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/*
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* CORE DPLL (DPLL3) M2 divider rate programming functions
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*
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* These call into SRAM code to do the actual CM writes, since the SDRAM
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* is clocked from DPLL3.
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*/
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/**
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* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
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* @clk: struct clk * of DPLL to set
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* @rate: rounded target rate
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*
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* Program the DPLL M2 divider with the rounded target rate. Returns
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* -EINVAL upon error, or 0 upon success.
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*/
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int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 new_div = 0;
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u32 unlock_dll = 0;
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u32 c;
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unsigned long validrate, sdrcrate, _mpurate;
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struct omap_sdrc_params *sdrc_cs0;
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struct omap_sdrc_params *sdrc_cs1;
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int ret;
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unsigned long clkrate;
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if (!clk || !rate)
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return -EINVAL;
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new_div = DIV_ROUND_UP(parent_rate, rate);
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validrate = parent_rate / new_div;
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if (validrate != rate)
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return -EINVAL;
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sdrcrate = clk_get_rate(sdrc_ick_p);
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clkrate = clk_hw_get_rate(hw);
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if (rate > clkrate)
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sdrcrate <<= ((rate / clkrate) >> 1);
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else
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sdrcrate >>= ((clkrate / rate) >> 1);
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ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
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if (ret)
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return -EINVAL;
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if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
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pr_debug("clock: will unlock SDRC DLL\n");
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unlock_dll = 1;
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}
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/*
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* XXX This only needs to be done when the CPU frequency changes
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*/
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_mpurate = clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
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c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
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c += 1; /* for safety */
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c *= SDRC_MPURATE_LOOPS;
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c >>= SDRC_MPURATE_SCALE;
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if (c == 0)
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c = 1;
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
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clkrate, validrate);
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pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
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if (sdrc_cs1)
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pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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if (sdrc_cs1)
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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else
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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0, 0, 0, 0);
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return 0;
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}
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@ -211,35 +211,10 @@ static inline int omap243x_sram_init(void)
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#ifdef CONFIG_ARCH_OMAP3
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static u32 (*_omap3_sram_configure_core_dpll)(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
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{
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BUG_ON(!_omap3_sram_configure_core_dpll);
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return _omap3_sram_configure_core_dpll(
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m2, unlock_dll, f, inc,
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sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
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sdrc_actim_ctrl_b_0, sdrc_mr_0,
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sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
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sdrc_actim_ctrl_b_1, sdrc_mr_1);
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}
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void omap3_sram_restore_context(void)
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{
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omap_sram_reset();
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_omap3_sram_configure_core_dpll =
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omap_sram_push(omap3_sram_configure_core_dpll,
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omap3_sram_configure_core_dpll_sz);
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omap_push_sram_idle();
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}
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@ -15,12 +15,6 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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extern void omap3_sram_restore_context(void);
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/* Do not use these */
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@ -52,14 +46,6 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#ifdef CONFIG_PM
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extern void omap_push_sram_idle(void);
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#else
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@ -1,346 +0,0 @@
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/*
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* linux/arch/arm/mach-omap3/sram.S
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
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* Copyright (C) 2008 Nokia Corporation
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*
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* Rajendra Nayak <rnayak@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "soc.h"
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#include "iomap.h"
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#include "sdrc.h"
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#include "cm3xxx.h"
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/*
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* This file needs be built unconditionally as ARM to interoperate correctly
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* with non-Thumb-2-capable firmware.
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*/
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.arm
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.text
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/* r1 parameters */
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#define SDRC_NO_UNLOCK_DLL 0x0
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#define SDRC_UNLOCK_DLL 0x1
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/* SDRC_DLLA_CTRL bit settings */
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#define FIXEDDELAY_SHIFT 24
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#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
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#define DLLIDLE_MASK 0x4
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/*
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* SDRC_DLLA_CTRL default values: TI hardware team indicates that
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* FIXEDDELAY should be initialized to 0xf. This apparently was
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* empirically determined during process testing, so no derivation
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* was provided.
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*/
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#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
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/* SDRC_DLLA_STATUS bit settings */
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#define LOCKSTATUS_MASK 0x4
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/* SDRC_POWER bit settings */
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#define SRFRONIDLEREQ_MASK 0x40
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/* CM_IDLEST1_CORE bit settings */
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#define ST_SDRC_MASK 0x2
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/* CM_ICLKEN1_CORE bit settings */
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#define EN_SDRC_MASK 0x2
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/* CM_CLKSEL1_PLL bit settings */
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#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
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/*
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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*
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* Params passed in registers:
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* r0 = new M2 divider setting (only 1 and 2 supported right now)
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* r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r2 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r3 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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* Params passed via the stack. The needed params will be copied in SRAM
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* before use by the code in SRAM (SDRAM is not accessible during SDRC
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* reconfiguration):
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* new SDRC_RFR_CTRL_0 register contents
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* new SDRC_ACTIM_CTRL_A_0 register contents
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* new SDRC_ACTIM_CTRL_B_0 register contents
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* new SDRC_MR_0 register value
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* new SDRC_RFR_CTRL_1 register contents
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* new SDRC_ACTIM_CTRL_A_1 register contents
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* new SDRC_ACTIM_CTRL_B_1 register contents
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* new SDRC_MR_1 register value
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*
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* If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
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* the SDRC CS1 registers
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*
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* NOTE: This code no longer attempts to program the SDRC AC timing and MR
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* registers. This is because the code currently cannot ensure that all
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* L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
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* SDRAM when the registers are written. If the registers are changed while
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* an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
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* may enter an unpredictable state. In the future, the intent is to
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* re-enable this code in cases where we can ensure that no initiators are
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* touching the SDRAM. Until that time, users who know that their use case
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* can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
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* option.
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*
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* Richard Woodruff notes that any changes to this code must be carefully
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* audited and tested to ensure that they don't cause a TLB miss while
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* the SDRAM is inaccessible. Such a situation will crash the system
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* since it will cause the ARM MMU to attempt to walk the page tables.
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* These crashes may be intermittent.
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*/
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.align 3
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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@ pull the extra args off the stack
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@ and store them in SRAM
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/*
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* PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
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* in Thumb-2: use a r7 as a base instead.
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* Be careful not to clobber r7 when maintaing this file.
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*/
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THUMB( adr r7, omap3_sram_configure_core_dpll )
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.macro strtext Rt:req, label:req
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ARM( str \Rt, \label )
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THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
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.endm
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ldr r4, [sp, #52]
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strtext r4, omap_sdrc_rfr_ctrl_0_val
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ldr r4, [sp, #56]
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strtext r4, omap_sdrc_actim_ctrl_a_0_val
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ldr r4, [sp, #60]
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strtext r4, omap_sdrc_actim_ctrl_b_0_val
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ldr r4, [sp, #64]
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strtext r4, omap_sdrc_mr_0_val
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ldr r4, [sp, #68]
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strtext r4, omap_sdrc_rfr_ctrl_1_val
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cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
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beq skip_cs1_params @ do not use cs1 params
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ldr r4, [sp, #72]
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strtext r4, omap_sdrc_actim_ctrl_a_1_val
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ldr r4, [sp, #76]
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strtext r4, omap_sdrc_actim_ctrl_b_1_val
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ldr r4, [sp, #80]
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strtext r4, omap_sdrc_mr_1_val
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skip_cs1_params:
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mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
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bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
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mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
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dsb @ flush buffered writes to interconnect
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isb @ prevent speculative exec past here
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cmp r3, #1 @ if increasing SDRC clk rate,
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bleq configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
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bl configure_core_dpll @ change the DPLL3 M2 divider
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mov r12, r2
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bl wait_clk_stable @ wait for SDRC to stabilize
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bl enable_sdrc @ take SDRC out of idle
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cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #1 @ if increasing SDRC clk rate,
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beq return_to_sdram @ return to SDRAM code, otherwise,
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bl configure_sdrc @ reprogram SDRC regs now
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return_to_sdram:
|
||||
mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
|
||||
isb @ prevent speculative exec past here
|
||||
mov r0, #0 @ return value
|
||||
ldmfd sp!, {r1-r12, pc} @ restore regs and return
|
||||
unlock_dll:
|
||||
ldr r11, omap3_sdrc_dlla_ctrl
|
||||
ldr r12, [r11]
|
||||
bic r12, r12, #FIXEDDELAY_MASK
|
||||
orr r12, r12, #FIXEDDELAY_DEFAULT
|
||||
orr r12, r12, #DLLIDLE_MASK
|
||||
str r12, [r11] @ (no OCP barrier needed)
|
||||
bx lr
|
||||
lock_dll:
|
||||
ldr r11, omap3_sdrc_dlla_ctrl
|
||||
ldr r12, [r11]
|
||||
bic r12, r12, #DLLIDLE_MASK
|
||||
str r12, [r11] @ (no OCP barrier needed)
|
||||
bx lr
|
||||
sdram_in_selfrefresh:
|
||||
ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
|
||||
ldr r12, [r11] @ read the contents of SDRC_POWER
|
||||
mov r9, r12 @ keep a copy of SDRC_POWER bits
|
||||
orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
|
||||
str r12, [r11] @ write back to SDRC_POWER register
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
idle_sdrc:
|
||||
ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
|
||||
ldr r12, [r11]
|
||||
bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
|
||||
str r12, [r11]
|
||||
wait_sdrc_idle:
|
||||
ldr r11, omap3_cm_idlest1_core
|
||||
ldr r12, [r11]
|
||||
and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
|
||||
cmp r12, #ST_SDRC_MASK
|
||||
bne wait_sdrc_idle
|
||||
bx lr
|
||||
configure_core_dpll:
|
||||
ldr r11, omap3_cm_clksel1_pll
|
||||
ldr r12, [r11]
|
||||
ldr r10, core_m2_mask_val @ modify m2 for core dpll
|
||||
and r12, r12, r10
|
||||
orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
|
||||
str r12, [r11]
|
||||
ldr r12, [r11] @ posted-write barrier for CM
|
||||
bx lr
|
||||
wait_clk_stable:
|
||||
subs r12, r12, #1
|
||||
bne wait_clk_stable
|
||||
bx lr
|
||||
enable_sdrc:
|
||||
ldr r11, omap3_cm_iclken1_core
|
||||
ldr r12, [r11]
|
||||
orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
|
||||
str r12, [r11]
|
||||
wait_sdrc_idle1:
|
||||
ldr r11, omap3_cm_idlest1_core
|
||||
ldr r12, [r11]
|
||||
and r12, r12, #ST_SDRC_MASK
|
||||
cmp r12, #0
|
||||
bne wait_sdrc_idle1
|
||||
restore_sdrc_power_val:
|
||||
ldr r11, omap3_sdrc_power
|
||||
str r9, [r11] @ restore SDRC_POWER, no barrier needed
|
||||
bx lr
|
||||
wait_dll_lock:
|
||||
ldr r11, omap3_sdrc_dlla_status
|
||||
ldr r12, [r11]
|
||||
and r12, r12, #LOCKSTATUS_MASK
|
||||
cmp r12, #LOCKSTATUS_MASK
|
||||
bne wait_dll_lock
|
||||
bx lr
|
||||
wait_dll_unlock:
|
||||
ldr r11, omap3_sdrc_dlla_status
|
||||
ldr r12, [r11]
|
||||
and r12, r12, #LOCKSTATUS_MASK
|
||||
cmp r12, #0x0
|
||||
bne wait_dll_unlock
|
||||
bx lr
|
||||
configure_sdrc:
|
||||
ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
|
||||
str r12, [r11] @ store
|
||||
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_0_val
|
||||
ldr r11, omap3_sdrc_mr_0
|
||||
str r12, [r11]
|
||||
#endif
|
||||
ldr r12, omap_sdrc_rfr_ctrl_1_val
|
||||
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
|
||||
beq skip_cs1_prog @ do not program cs1 params
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_1
|
||||
str r12, [r11]
|
||||
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_1_val
|
||||
ldr r11, omap3_sdrc_mr_1
|
||||
str r12, [r11]
|
||||
#endif
|
||||
skip_cs1_prog:
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
bx lr
|
||||
|
||||
.align
|
||||
omap3_sdrc_power:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
|
||||
omap3_cm_clksel1_pll:
|
||||
.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
|
||||
omap3_cm_idlest1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
|
||||
omap3_cm_iclken1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
|
||||
|
||||
omap3_sdrc_rfr_ctrl_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
|
||||
omap3_sdrc_rfr_ctrl_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
|
||||
omap3_sdrc_actim_ctrl_a_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
|
||||
omap3_sdrc_actim_ctrl_a_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
|
||||
omap3_sdrc_actim_ctrl_b_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
|
||||
omap3_sdrc_actim_ctrl_b_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
|
||||
omap3_sdrc_mr_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
|
||||
omap3_sdrc_mr_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
|
||||
omap_sdrc_rfr_ctrl_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_rfr_ctrl_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_1_val:
|
||||
.word 0xDEADBEEF
|
||||
|
||||
omap3_sdrc_dlla_status:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
|
||||
omap3_sdrc_dlla_ctrl:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
|
||||
core_m2_mask_val:
|
||||
.word 0x07FFFFFF
|
||||
ENDPROC(omap3_sram_configure_core_dpll)
|
||||
|
||||
ENTRY(omap3_sram_configure_core_dpll_sz)
|
||||
.word . - omap3_sram_configure_core_dpll
|
||||
|
||||
Loading…
Reference in New Issue
Block a user