mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 17:46:40 +07:00
ARM: S3C24XX: move s3c2412 irq init to common code
Base for further cleanups Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
592957085e
commit
d3d5a2c9e6
@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
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obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
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obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o irq-s3c2412.o clock-s3c2412.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o
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obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o
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obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
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obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
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@ -1,192 +0,0 @@
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/* linux/arch/arm/mach-s3c2412/irq.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/irq.h>
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#include <plat/pm.h>
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#include "s3c2412-power.h"
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
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/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
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* having them turn up in both the INT* and the EINT* registers. Whilst
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* both show the status, they both now need to be acked when the IRQs
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* go off.
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*/
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static void
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s3c2412_irq_mask(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask | bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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}
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static inline void
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s3c2412_irq_ack(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static inline void
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s3c2412_irq_maskack(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static void
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s3c2412_irq_unmask(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask & ~bitval, S3C2412_EINTMASK);
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask & ~bitval, S3C2410_INTMSK);
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}
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static struct irq_chip s3c2412_irq_eint0t4 = {
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.irq_ack = s3c2412_irq_ack,
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.irq_mask = s3c2412_irq_mask,
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.irq_unmask = s3c2412_irq_unmask,
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.irq_set_wake = s3c_irq_wake,
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.irq_set_type = s3c_irqext_type,
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};
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#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
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/* CF and SDI sub interrupts */
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static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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if (subsrc & INTBIT(IRQ_S3C2412_SDI))
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generic_handle_irq(IRQ_S3C2412_SDI);
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if (subsrc & INTBIT(IRQ_S3C2412_CF))
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generic_handle_irq(IRQ_S3C2412_CF);
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}
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#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
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#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
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static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static struct irq_chip s3c2412_irq_cfsdi = {
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.name = "s3c2412-cfsdi",
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.irq_ack = s3c2412_irq_cfsdi_ack,
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.irq_mask = s3c2412_irq_cfsdi_mask,
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.irq_unmask = s3c2412_irq_cfsdi_unmask,
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};
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static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
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{
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unsigned int irqno;
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for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
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handle_edge_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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/* add demux support for CF/SDI */
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irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
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for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct subsys_interface s3c2412_irq_interface = {
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.name = "s3c2412_irq",
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.subsys = &s3c2412_subsys,
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.add_dev = s3c2412_irq_add,
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};
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static int s3c2412_irq_init(void)
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{
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return subsys_interface_register(&s3c2412_irq_interface);
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}
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arch_initcall(s3c2412_irq_init);
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@ -626,6 +626,160 @@ void __init s3c24xx_init_irq(void)
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s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
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}
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#ifdef CONFIG_CPU_S3C2412
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
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/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
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* having them turn up in both the INT* and the EINT* registers. Whilst
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* both show the status, they both now need to be acked when the IRQs
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* go off.
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*/
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static void
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s3c2412_irq_mask(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask | bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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}
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static inline void
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s3c2412_irq_ack(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static inline void
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s3c2412_irq_maskack(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static void
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s3c2412_irq_unmask(struct irq_data *data)
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{
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unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask & ~bitval, S3C2412_EINTMASK);
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask & ~bitval, S3C2410_INTMSK);
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}
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static struct irq_chip s3c2412_irq_eint0t4 = {
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.irq_ack = s3c2412_irq_ack,
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.irq_mask = s3c2412_irq_mask,
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.irq_unmask = s3c2412_irq_unmask,
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.irq_set_wake = s3c_irq_wake,
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.irq_set_type = s3c_irqext_type,
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};
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#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
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/* CF and SDI sub interrupts */
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static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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if (subsrc & INTBIT(IRQ_S3C2412_SDI))
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generic_handle_irq(IRQ_S3C2412_SDI);
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if (subsrc & INTBIT(IRQ_S3C2412_CF))
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generic_handle_irq(IRQ_S3C2412_CF);
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}
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#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
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#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
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static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static struct irq_chip s3c2412_irq_cfsdi = {
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.name = "s3c2412-cfsdi",
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.irq_ack = s3c2412_irq_cfsdi_ack,
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.irq_mask = s3c2412_irq_cfsdi_mask,
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.irq_unmask = s3c2412_irq_cfsdi_unmask,
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};
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static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
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{
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unsigned int irqno;
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for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
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handle_edge_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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/* add demux support for CF/SDI */
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irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
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for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct subsys_interface s3c2412_irq_interface = {
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.name = "s3c2412_irq",
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.subsys = &s3c2412_subsys,
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.add_dev = s3c2412_irq_add,
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};
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static int s3c2412_irq_init(void)
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{
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return subsys_interface_register(&s3c2412_irq_interface);
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}
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arch_initcall(s3c2412_irq_init);
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#endif
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#ifdef CONFIG_CPU_S3C2416
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static struct s3c_irq_data init_s3c2416base[32] = {
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
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