AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-01-27 08:02:18 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

i.MX device tree changes for 5.8:

Browse Source 
- A series from Anson Huang updating SRC devices to match bindings
   schema definition.
 - Correct CPU supply name and add cpu1 supply for i.MX7D.
 - Convert thermal device to use nvmem interface to get fuse data
   for imx6qdl and imx6sl.
 - A series from Tim Harvey to update imx6qdl-gw devices, adding support
   of LSM9DS1 IIO imu/magn, USB OTG, bcm4330-bt, etc.
 - Add input MUX for ENET2 MDIO into IMX7D pin functions.
 - Misc random device addition or update.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl7IhYQUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM5Bvwf8Cy/gm3ezs2OmjtdF3jql86qo7tqk
 nUwPDnRhlPYInN8yKlipMsYn2yupCPSwENGYwxLculwsHyQ7RNEI8a1jY2zEkdh9
 +IoZCNeOxOk40iQoCtaxBAJVz73BY8ptdKgfKL44xQ32e4oVQrgw1iAPdNS60yzl
 5TRXxghYnfeRC5c7ZKKEF0X74RzWb/zwEWAcs3yczuPzQGAtcBmYTG8b/y+/HNT0
 oTTcnN+clw48xAPuq6/8nMseVMLqTzyyBQpn/TI78LWGfBtaTIv6l7pjZBquhSGi
 +QYKHgbC3POv8TYWGu+csqFfQvbfeiO/HEHFKPcvJ8O+QoRMB9nvejn42Q==
 =I7h9
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree changes for 5.8:

- A series from Anson Huang updating SRC devices to match bindings
  schema definition.
- Correct CPU supply name and add cpu1 supply for i.MX7D.
- Convert thermal device to use nvmem interface to get fuse data
  for imx6qdl and imx6sl.
- A series from Tim Harvey to update imx6qdl-gw devices, adding support
  of LSM9DS1 IIO imu/magn, USB OTG, bcm4330-bt, etc.
- Add input MUX for ENET2 MDIO into IMX7D pin functions.
- Misc random device addition or update.

* tag 'imx-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (22 commits)
  ARM: dts: imx53-cx9020: Group port definitions for the dvi-converter
  ARM: dts: imx5: make src node name generic
  ARM: dts: imx50: Add src node interrupt
  ARM: dts: imx: make src node name generic
  ARM: dts: imx7d-pinfunc: add input mux for ENET2 mdio
  ARM: dts: imx6sl: Use nvmem interface to get fuse data
  ARM: dts: imx6qdl: Use nvmem interface to get fuse data
  ARM: dts: imx6qdl-gw5910: fix wlan regulator
  ARM: dts: imx6qdl-gw5910: add support for bcm4330-bt
  ARM: dts: imx6qdl-gw5904: add lsm9ds1 iio imu/magn support
  ARM: dts: imx6qdl-gw560x: add lsm9ds1 iio imu/magn support
  ARM: dts: imx53: Add src node interrupt
  ARM: dts: imx51: Add src node interrupt
  ARM: dts: imx50: Remove unused iomuxc-gpr node
  ARM: dts: imx6qdl-gw552x: add USB OTG support
  ARM: dts: imx6-sr-som: add ethernet PHY configuration
  arm: dts: ls1021atwr: Add QSPI node properties
  ARM: dts: e60k02: add interrupt for PMIC
  ARM: dts: colibri: introduce device trees with UHS-I support
  ARM: dts: imx7d: Add cpu1 supply
  ...

Link: https://lore.kernel.org/r/20200523032516.11016-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-26 00:22:39 +02:00
commit d39b6ae4be
30 changed files with 384 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -416,6 +416,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-colibri-eval-v3.dtb \
imx6dl-colibri-v1_1-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \

2
arch/arm/boot/dts/e60k02.dtsi
View File

@ -117,6 +117,8 @@ &i2c3 {
ricoh619: pmic@32 {
compatible = "ricoh,rc5t619";
reg = <0x32>;
interrupt-parent = <&gpio5>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
system-power-controller;
regulators {

8
arch/arm/boot/dts/imx50.dtsi
View File

@ -288,11 +288,6 @@ iomuxc: iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
gpr: iomuxc-gpr@53fa8000 {
compatible = "fsl,imx50-iomuxc-gpr", "syscon";
reg = <0x53fa8000 0xc>;
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
@ -333,9 +328,10 @@ uart2: serial@53fc0000 {
status = "disabled";
};
src: src@53fd0000 {
src: reset-controller@53fd0000 {
compatible = "fsl,imx50-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};

3
arch/arm/boot/dts/imx51.dtsi
View File

@ -439,9 +439,10 @@ uart2: serial@73fc0000 {
status = "disabled";
};
src: src@73fd0000 {
src: reset-controller@73fd0000 {
compatible = "fsl,imx51-src";
reg = <0x73fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};

25
arch/arm/boot/dts/imx53-cx9020.dts
View File

@ -59,23 +59,26 @@ dvi_connector_in: endpoint {
};
dvi-converter {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,tfp410";
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tfp410_in: endpoint {
remote-endpoint = <&display0_out>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};

3
arch/arm/boot/dts/imx53.dtsi
View File

@ -588,9 +588,10 @@ can2: can@53fcc000 {
status = "disabled";
};
src: src@53fd0000 {
src: reset-controller@53fd0000 {
compatible = "fsl,imx53-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};

31
arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2020 Toradex
*/
/dts-v1/;
#include "imx6dl-colibri-eval-v3.dts"
#include "imx6qdl-colibri-v1_1-uhs.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3";
compatible = "toradex,colibri_imx6dl-v1_1-eval-v3",
"toradex,colibri_imx6dl-v1_1",
"toradex,colibri_imx6dl-eval-v3",
"toradex,colibri_imx6dl",
"fsl,imx6dl";
};
/* Colibri MMC */
&usdhc1 {
status = "okay";
/*
* Please make sure your carrier board does not pull-up any of
* the MMC/SD signals to 3.3 volt before attempting to activate
* UHS-I support.
* To let signaling voltage be changed to 1.8V, please
* delete no-1-8-v property (example below):
* /delete-property/no-1-8-v;
*/
};

115
arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
View File

@ -22,6 +22,53 @@ clk_ext_audio_codec: clock-codec {
clock-frequency = <24000000>;
};
display_bl: display-bl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
lcd_display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_lcdif>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel {
compatible = "edt,etm0700g0edh6";
ddc-i2c-bus = <&i2c2>;
backlight = <&display_bl>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx-sgtl5000";
@ -65,6 +112,15 @@ sgtl5000: codec@a {
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&sw2_reg>;
};
touchscreen@38 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
compatible = "edt,edt-ft5406";
reg = <0x38>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
};
};
&iomuxc {
@ -77,9 +133,7 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
@ -132,6 +186,52 @@ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
>;
};
pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
>;
};
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_touchscreen: touchscreen-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1
>;
};
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
@ -139,6 +239,10 @@ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@ -146,6 +250,13 @@ &pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <3>;
status = "okay";
};
&ssi1 {
status = "okay";
};

44
arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2020 Toradex
*/
&iomuxc {
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
>;
};
};
/* Colibri MMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
vmmc-supply = <&reg_module_3v3>;
vqmmc-supply = <&vgen3_reg>;
wakeup-source;
keep-power-in-suspend;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};

11
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View File

@ -193,7 +193,16 @@ vgen2_reg: vgen2 {
regulator-always-on;
};
/* vgen3: unused */
/*
* +V3.3_1.8_SD1 coming off VGEN3 and supplying
* the i.MX 6 NVCC_SD1.
*/
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;

14
arch/arm/boot/dts/imx6qdl-gw552x.dtsi
View File

@ -258,6 +258,14 @@ &usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_5p0v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
@ -359,6 +367,12 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0

31
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
View File

@ -295,6 +295,15 @@ sgtl5000: codec@a {
VDDIO-supply = <&reg_3p3v>;
};
magn@1c {
compatible = "st,lsm9ds1-magn";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
};
tca8418: keypad@34 {
compatible = "ti,tca8418";
pinctrl-names = "default";
@ -389,6 +398,16 @@ reg_3p0v: ldo4 {
};
};
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
st,drdy-int-pin = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
};
};
&i2c3 {
@ -609,6 +628,12 @@ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
>;
};
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
@ -616,6 +641,12 @@ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */

31
arch/arm/boot/dts/imx6qdl-gw5904.dtsi
View File

@ -248,6 +248,15 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
magn@1c {
compatible = "st,lsm9ds1-magn";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
};
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
@ -320,6 +329,16 @@ reg_3p0v: ldo4 {
};
};
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
st,drdy-int-pin = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
};
};
&i2c3 {
@ -501,6 +520,18 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_imu: imugrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */

35
arch/arm/boot/dts/imx6qdl-gw5910.dtsi
View File

@ -81,20 +81,6 @@ reg_wl: regulator-wl {
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_bt: regulator-bt {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_bt>;
compatible = "regulator-fixed";
regulator-name = "bt";
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
@ -231,9 +217,14 @@ &uart3 {
/* Sterling-LWB Bluetooth */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
};
};
/* GPS */
@ -259,7 +250,7 @@ &usbh1 {
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_3p3v>;
vmmc-supply = <&reg_wl>;
non-removable;
bus-width = <4>;
status = "okay";
@ -288,6 +279,12 @@ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
>;
};
pinctrl_bten: btengrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
>;
};
pinctrl_ecspi3: escpi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
@ -393,12 +390,6 @@ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_bt: regbtgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
>;
};
pinctrl_reg_wl: regwlgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1

11
arch/arm/boot/dts/imx6qdl-sr-som.dtsi
View File

@ -53,10 +53,21 @@ vcc_3v3: regulator-vcc-3v3 {
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <125000000>;
};
};
};
&iomuxc {

13
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -74,7 +74,8 @@ tempmon: tempmon {
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
@ -857,7 +858,7 @@ epit2: epit@20d4000 { /* EPIT2 */
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@ -1171,6 +1172,14 @@ ocotp: ocotp-ctrl@21bc000 {
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
};
tzasc@21d0000 { /* TZASC1 */

13
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -98,7 +98,8 @@ tempmon: tempmon {
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
@ -677,7 +678,7 @@ epit2: epit@20d4000 {
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@ -961,6 +962,14 @@ ocotp: ocotp-ctrl@21bc000 {
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
};
audmux: audmux@21d8000 {

2
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -754,7 +754,7 @@ epit2: epit@20d4000 {
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -676,7 +676,7 @@ epit2: epit@20d4000 {
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6ul-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/imx7-tqma7.dtsi
View File

@ -16,7 +16,7 @@ memory@80000000 {
};
&cpu0 {
arm-supply = <&sw1a_reg>;
cpu-supply = <&sw1a_reg>;
};
&i2c1 {

4
arch/arm/boot/dts/imx7d-cl-som-imx7.dts
View File

@ -37,6 +37,10 @@ &cpu0 {
cpu-supply = <&sw1a_reg>;
};
&cpu1 {
cpu-supply = <&sw1a_reg>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;

4
arch/arm/boot/dts/imx7d-colibri.dtsi
View File

@ -13,6 +13,10 @@ memory@80000000 {
};
};
&cpu1 {
cpu-supply = <&reg_DCDC2>;
};
&gpmi {
status = "okay";
};

4
arch/arm/boot/dts/imx7d-nitrogen7.dts
View File

@ -121,6 +121,10 @@ &cpu0 {
cpu-supply = <&sw1a_reg>;
};
&cpu1 {
cpu-supply = <&sw1a_reg>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;

2
arch/arm/boot/dts/imx7d-pinfunc.h
View File

@ -592,7 +592,7 @@
#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0
#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1
#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0
#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3
#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0

4
arch/arm/boot/dts/imx7d-sdb.dts
View File

@ -162,6 +162,10 @@ &cpu0 {
cpu-supply = <&sw1a_reg>;
};
&cpu1 {
cpu-supply = <&sw1a_reg>;
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;

4
arch/arm/boot/dts/imx7d-tqma7.dtsi
View File

@ -9,3 +9,7 @@
#include "imx7d.dtsi"
#include "imx7-tqma7.dtsi"
&cpu1 {
cpu-supply = <&sw1a_reg>;
};

2
arch/arm/boot/dts/imx7d-zii-rmu2.dts
View File

@ -33,7 +33,7 @@ debug {
};
&cpu0 {
arm-supply = <&sw1a_reg>;
cpu-supply = <&sw1a_reg>;
};
&ecspi1 {

2
arch/arm/boot/dts/imx7d-zii-rpu2.dts
View File

@ -182,7 +182,7 @@ &adc2 {
};
&cpu0 {
arm-supply = <&sw1a_reg>;
cpu-supply = <&sw1a_reg>;
};
&clks {

2
arch/arm/boot/dts/imx7s.dtsi
View File

@ -624,7 +624,7 @@ clks: clock-controller@30380000 {
clock-names = "ckil", "osc";
};
src: src@30390000 {
src: reset-controller@30390000 {
compatible = "fsl,imx7d-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

14
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -242,6 +242,20 @@ &esdhc {
status = "okay";
};
&qspi {
status = "okay";
n25q128a130: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&sai1 {
status = "okay";
};