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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-19 03:26:23 +07:00
drm/nve0/fb/gddr5: not all memory partitions are created equal
As seen when comparing us vs nv on my GTX660. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs
parent
dd95c8f782
commit
d394fb12ec
@ -142,6 +142,7 @@ struct nouveau_ram {
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} rammap, ramcfg, timing;
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u32 freq;
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u32 mr[16];
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u32 mr1_nuts;
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};
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#endif
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@ -26,11 +26,11 @@
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#include "priv.h"
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int
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nouveau_gddr5_calc(struct nouveau_ram *ram)
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nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
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{
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struct nouveau_bios *bios = nouveau_bios(ram);
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int pd, lf, xd, vh, vr, vo;
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int WL, CL, WR, at, dt, ds;
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int WL, CL, WR, at[2], dt, ds;
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int rq = ram->freq < 1000000; /* XXX */
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switch (!!ram->ramcfg.data * ram->ramcfg.version) {
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@ -51,7 +51,8 @@ nouveau_gddr5_calc(struct nouveau_ram *ram)
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WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7;
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CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
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WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
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at = (nv_ro08(bios, ram->timing.data + 0x2e) & 0xc0) >> 6;
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at[0] = (nv_ro08(bios, ram->timing.data + 0x2e) & 0xc0) >> 6;
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at[1] = (nv_ro08(bios, ram->timing.data + 0x2e) & 0x30) >> 4;
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dt = nv_ro08(bios, ram->timing.data + 0x2e) & 0x03;
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ds = nv_ro08(bios, ram->timing.data + 0x2f) & 0x03;
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break;
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@ -71,10 +72,19 @@ nouveau_gddr5_calc(struct nouveau_ram *ram)
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ram->mr[1] &= ~0x0bf;
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ram->mr[1] |= (xd & 0x01) << 7;
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ram->mr[1] |= (at & 0x03) << 4;
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ram->mr[1] |= (at[0] & 0x03) << 4;
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ram->mr[1] |= (dt & 0x03) << 2;
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ram->mr[1] |= (ds & 0x03) << 0;
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/* this seems wrong, alternate field used for the broadcast
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* on nuts vs non-nuts configs.. meh, it matches for now.
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*/
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ram->mr1_nuts = ram->mr[1];
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if (nuts) {
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ram->mr[1] &= ~0x030;
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ram->mr[1] |= (at[1] & 0x03) << 4;
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}
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ram->mr[3] &= ~0x020;
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ram->mr[3] |= (rq & 0x01) << 5;
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@ -34,7 +34,7 @@ extern struct nouveau_oclass nvc0_ram_oclass;
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extern struct nouveau_oclass nve0_ram_oclass;
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int nouveau_sddr3_calc(struct nouveau_ram *ram);
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int nouveau_gddr5_calc(struct nouveau_ram *ram);
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int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts);
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#define nouveau_fb_create(p,e,c,d) \
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nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
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@ -103,7 +103,9 @@ struct nve0_ramfuc {
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struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
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struct ramfuc_reg r_0x62c000;
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struct ramfuc_reg r_0x10f200;
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struct ramfuc_reg r_0x10f210;
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struct ramfuc_reg r_0x10f310;
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struct ramfuc_reg r_0x10f314;
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@ -123,6 +125,11 @@ struct nve0_ramfuc {
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struct nve0_ram {
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struct nouveau_ram base;
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struct nve0_ramfuc fuc;
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u32 parts;
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u32 pmask;
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u32 pnuts;
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int from;
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int mode;
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int N1, fN1, M1, P1;
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@ -136,16 +143,13 @@ static void
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nve0_ram_train(struct nve0_ramfuc *fuc, u32 magic)
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{
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struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
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struct nouveau_fb *pfb = nouveau_fb(ram);
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u32 part = nv_rd32(pfb, 0x022438), i;
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u32 mask = nv_rd32(pfb, 0x022554);
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u32 addr = 0x110974;
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u32 addr = 0x110974, i;
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ram_mask(fuc, 0x10f910, 0xbc0e0000, magic);
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ram_mask(fuc, 0x10f914, 0xbc0e0000, magic);
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for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
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if (mask & (1 << i))
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for (i = 0; (magic & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
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if (ram->pmask & (1 << i))
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continue;
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ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
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}
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@ -222,6 +226,28 @@ r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg)
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ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
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}
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static void
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nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
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u32 _mask, u32 _data, u32 _copy)
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{
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struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
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struct ramfuc *fuc = &ram->fuc.base;
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u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
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u32 mask = _mask | _copy;
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u32 data = (_data & _mask) | (reg->data & _copy);
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u32 i;
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for (i = 0; i < 16; i++, addr += 0x1000) {
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if (ram->pnuts & (1 << i)) {
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u32 prev = nv_rd32(priv, addr);
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u32 next = (prev & ~mask) | data;
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nouveau_memx_wr32(fuc->memx, addr, next);
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}
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}
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}
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#define ram_nuts(s,r,m,d,c) \
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nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
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static int
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nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
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{
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@ -233,14 +259,16 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
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const u32 timing = ram->base.timing.data;
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int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
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int mv = 1; /*XXX*/
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u32 mask, data;
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u32 mask, data, i;
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ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
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ram_wr32(fuc, 0x62c000, 0x0f0f0000);
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/* MR1: turn termination on early, for some reason.. */
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if ((ram->base.mr[1] & 0x03c) != 0x030)
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if ((ram->base.mr[1] & 0x03c) != 0x030) {
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ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
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ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
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}
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if (vc == 1 && ram_have(fuc, gpio2E)) {
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u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
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@ -546,6 +574,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
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ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
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ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
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ram_nsec(fuc, 1000);
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ram_nuts(ram, 0x10f200, 0x00808800, 0x00000000, 0x00808800);
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data = ram_rd32(fuc, 0x10f978);
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data &= ~0x00046144;
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@ -603,6 +632,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
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else
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data = 0x00000000;
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ram_mask(fuc, 0x10f200, 0x00000800, data);
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ram_nuts(ram, 0x10f200, 0x00808800, data, 0x00808800);
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return 0;
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}
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@ -980,7 +1010,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ret = nve0_ram_calc_sddr3(pfb, freq);
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break;
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case NV_MEM_TYPE_GDDR5:
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ret = nouveau_gddr5_calc(&ram->base);
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ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
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if (ret == 0)
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ret = nve0_ram_calc_gddr5(pfb, freq);
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break;
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@ -1109,7 +1139,8 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_gpio *gpio = nouveau_gpio(pfb);
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struct dcb_gpio_func func;
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struct nve0_ram *ram;
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int ret;
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int ret, i;
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u32 tmp;
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ret = nvc0_ram_create(parent, engine, oclass, &ram);
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*pobject = nv_object(ram);
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@ -1128,6 +1159,25 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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break;
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}
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/* calculate a mask of differently configured memory partitions,
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* because, of course reclocking wasn't complicated enough
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* already without having to treat some of them differently to
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* the others....
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*/
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ram->parts = nv_rd32(pfb, 0x022438);
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ram->pmask = nv_rd32(pfb, 0x022554);
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ram->pnuts = 0;
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for (i = 0, tmp = 0; i < ram->parts; i++) {
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if (!(ram->pmask & (1 << i))) {
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u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
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if (tmp && tmp != cfg1) {
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ram->pnuts |= (1 << i);
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continue;
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}
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tmp = cfg1;
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}
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}
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// parse bios data for both pll's
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ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
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if (ret) {
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