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ARM: lpc32xx: clean up header files
All device drivers have stopped relying on mach/*.h headers, so move the remaining headers into arch/arm/mach-lpc32xx/lpc32xx.h to prepare for multiplatform builds. The mach/entry-macro.S file has been unused for a long time now and can simply get removed. Link: https://lore.kernel.org/r/20190809144043.476786-13-arnd@arndb.de Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -13,8 +13,7 @@
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#include <asm/mach/map.h>
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#include <asm/system_info.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "lpc32xx.h"
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#include "common.h"
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/*
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* arch/arm/mach-lpc32xx/include/mach/entry-macro.S
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*/
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
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.endm
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/*
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* Return IRQ number in irqnr. Also return processor Z flag status in CPSR
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* as set if an interrupt is pending.
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #31
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teq \irqstat, #0
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.endm
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@ -1,25 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* arch/arm/mach-lpc32xx/include/mach/hardware.h
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*
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* Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/*
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* Start of virtual addresses for IO devices
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*/
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#define IO_BASE 0xF0000000
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/*
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* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
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*/
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#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
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IO_BASE)
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#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
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#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
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#endif
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@ -12,15 +12,13 @@
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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/*
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* Uncompress output is hardcoded to standard UART 5
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*/
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#define UART_FIFO_CTL_TX_RESET (1 << 2)
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#define UART_STATUS_TX_MT (1 << 6)
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#define LPC32XX_UART5_BASE 0x40090000
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#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
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@ -7,8 +7,8 @@
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* Copyright (C) 2010 NXP Semiconductors
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*/
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#ifndef __ASM_ARCH_PLATFORM_H
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#define __ASM_ARCH_PLATFORM_H
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#ifndef __ARM_LPC32XX_H
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#define __ARM_LPC32XX_H
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#define _SBF(f, v) ((v) << (f))
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#define _BIT(n) _SBF(n, 1)
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@ -700,4 +700,18 @@
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#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
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#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
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/*
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* Start of virtual addresses for IO devices
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*/
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#define IO_BASE 0xF0000000
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/*
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* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
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*/
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#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
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IO_BASE)
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#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
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#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
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#endif
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@ -70,8 +70,7 @@
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "lpc32xx.h"
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#include "common.h"
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#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
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@ -16,8 +16,7 @@
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "lpc32xx.h"
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#include "common.h"
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#define LPC32XX_SUART_FIFO_SIZE 64
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@ -11,8 +11,7 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/platform.h>
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#include <mach/hardware.h>
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#include "lpc32xx.h"
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/* Using named register defines makes the code easier to follow */
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#define WORK1_REG r0
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