AuxXxilium/linux_dsm_epyc7002
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  MIPS: Oprofile: Fix Loongson irq handler
  MIPS: N32: Use compat version for sys_ppoll.
  MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
This commit is contained in:
Linus Torvalds 2010-05-16 11:11:31 -07:00
commit d34e14f690
4 changed files with 21 additions and 7 deletions
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9
arch/mips/include/asm/mipsregs.h
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@ -134,6 +134,12 @@
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
/*
* Bits 18 - 20 of the FPU Status Register will be read as 0,
* and should be written as zero.
*/
#define FPU_CSR_RSVD 0x001c0000
/* /*
* X the exception cause indicator * X the exception cause indicator
* E the exception enable * E the exception enable
@ -161,7 +167,8 @@
#define FPU_CSR_UDF_S 0x00000008 #define FPU_CSR_UDF_S 0x00000008
#define FPU_CSR_INE_S 0x00000004 #define FPU_CSR_INE_S 0x00000004
/* rounding mode */ /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
#define FPU_CSR_RM 0x00000003
#define FPU_CSR_RN 0x0 /* nearest */ #define FPU_CSR_RN 0x0 /* nearest */
#define FPU_CSR_RZ 0x1 /* towards zero */ #define FPU_CSR_RZ 0x1 /* towards zero */
#define FPU_CSR_RU 0x2 /* towards +Infinity */ #define FPU_CSR_RU 0x2 /* towards +Infinity */

2
arch/mips/kernel/scall64-n32.S
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@ -385,7 +385,7 @@ EXPORT(sysn32_call_table)
PTR sys_fchmodat PTR sys_fchmodat
PTR sys_faccessat PTR sys_faccessat
PTR compat_sys_pselect6 PTR compat_sys_pselect6
PTR sys_ppoll /* 6265 */ PTR compat_sys_ppoll /* 6265 */
PTR sys_unshare PTR sys_unshare
PTR sys_splice PTR sys_splice
PTR sys_sync_file_range PTR sys_sync_file_range

15
arch/mips/math-emu/cp1emu.c
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@ -78,6 +78,9 @@ DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
#define FPCREG_RID 0 /* $0 = revision id */ #define FPCREG_RID 0 /* $0 = revision id */
#define FPCREG_CSR 31 /* $31 = csr */ #define FPCREG_CSR 31 /* $31 = csr */
/* Determine rounding mode from the RM bits of the FCSR */
#define modeindex(v) ((v) & FPU_CSR_RM)
/* Convert Mips rounding mode (0..3) to IEEE library modes. */ /* Convert Mips rounding mode (0..3) to IEEE library modes. */
static const unsigned char ieee_rm[4] = { static const unsigned char ieee_rm[4] = {
[FPU_CSR_RN] = IEEE754_RN, [FPU_CSR_RN] = IEEE754_RN,
@ -384,10 +387,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
(void *) (xcp->cp0_epc), (void *) (xcp->cp0_epc),
MIPSInst_RT(ir), value); MIPSInst_RT(ir), value);
#endif #endif
value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); /*
/* convert to ieee library modes */ * Don't write reserved bits,
ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; * and convert to ieee library modes
*/
ctx->fcr31 = (value &
~(FPU_CSR_RSVD | FPU_CSR_RM)) |
ieee_rm[modeindex(value)];
} }
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
return SIGFPE; return SIGFPE;

2
arch/mips/oprofile/op_model_loongson2.c
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@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
*/ */
/* Check whether the irq belongs to me */ /* Check whether the irq belongs to me */
enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
if (!enabled) if (!enabled)
return IRQ_NONE; return IRQ_NONE;
enabled = reg.cnt1_enabled | reg.cnt2_enabled; enabled = reg.cnt1_enabled | reg.cnt2_enabled;