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drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
v2: fix register access Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Ken Wang <ken.wang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
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adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
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adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
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adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
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adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
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adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
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adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
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adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
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/* Primitive Buffer */
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r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
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@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
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amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
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amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
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PACKET3_DMA_DATA_DST_SEL(1) |
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PACKET3_DMA_DATA_SRC_SEL(2)));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
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amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
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adev->gfx.ngg.gds_reserve_size);
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gfx_v9_0_write_data_to_reg(ring, 0, false,
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SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
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