mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 08:46:41 +07:00
drm/nv10: Fix up switching of NV10TCL_DMA_VTXBUF.
Not very nice, but I don't think there's a simpler workaround. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Francisco Jerez
Ben Skeggs
parent
308dcebac7
commit
d2f4e89254
@ -220,28 +220,21 @@
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# define NV_PGRAPH_INTR_ERROR (1<<20)
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#define NV10_PGRAPH_CTX_CONTROL 0x00400144
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#define NV10_PGRAPH_CTX_USER 0x00400148
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#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
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#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
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#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
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#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
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#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
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#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i))
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#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
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#define NV10_PGRAPH_CTX_CACHE1 0x00400160
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#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \
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+ 0x4*(i) + 0x20*(j))
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#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
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#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
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#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
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#define NV04_PGRAPH_CTX_CONTROL 0x00400170
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#define NV04_PGRAPH_CTX_USER 0x00400174
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#define NV04_PGRAPH_CTX_CACHE1 0x00400180
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#define NV10_PGRAPH_CTX_CACHE2 0x00400180
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#define NV03_PGRAPH_CTX_CONTROL 0x00400190
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#define NV03_PGRAPH_CTX_USER 0x00400194
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#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
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#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
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#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
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#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
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#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
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#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
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#define NV40_PGRAPH_CTXCTL_0304 0x00400304
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#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001
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#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308
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@ -356,9 +349,12 @@
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#define NV04_PGRAPH_FFINTFC_ST2 0x00400754
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#define NV10_PGRAPH_RDI_DATA 0x00400754
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#define NV04_PGRAPH_DMA_PITCH 0x00400760
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#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
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#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760
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#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
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#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
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#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
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#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768
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#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c
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#define NV10_PGRAPH_DMA_PITCH 0x00400770
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#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
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#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
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@ -43,51 +43,51 @@ struct pipe_state {
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};
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static int nv10_graph_ctx_regs[] = {
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NV10_PGRAPH_CTX_SWITCH1,
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NV10_PGRAPH_CTX_SWITCH2,
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NV10_PGRAPH_CTX_SWITCH3,
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NV10_PGRAPH_CTX_SWITCH4,
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NV10_PGRAPH_CTX_SWITCH5,
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NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
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NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
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NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
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NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
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NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
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0x00400164,
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0x00400184,
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0x004001a4,
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0x004001c4,
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0x004001e4,
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0x00400168,
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0x00400188,
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0x004001a8,
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0x004001c8,
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0x004001e8,
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0x0040016c,
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0x0040018c,
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0x004001ac,
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0x004001cc,
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0x004001ec,
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0x00400170,
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0x00400190,
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0x004001b0,
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0x004001d0,
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0x004001f0,
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0x00400174,
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0x00400194,
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0x004001b4,
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0x004001d4,
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0x004001f4,
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0x00400178,
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0x00400198,
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0x004001b8,
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0x004001d8,
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0x004001f8,
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0x0040017c,
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0x0040019c,
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0x004001bc,
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0x004001dc,
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0x004001fc,
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NV10_PGRAPH_CTX_SWITCH(0),
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NV10_PGRAPH_CTX_SWITCH(1),
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NV10_PGRAPH_CTX_SWITCH(2),
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NV10_PGRAPH_CTX_SWITCH(3),
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NV10_PGRAPH_CTX_SWITCH(4),
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NV10_PGRAPH_CTX_CACHE(0, 0),
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NV10_PGRAPH_CTX_CACHE(0, 1),
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NV10_PGRAPH_CTX_CACHE(0, 2),
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NV10_PGRAPH_CTX_CACHE(0, 3),
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NV10_PGRAPH_CTX_CACHE(0, 4),
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NV10_PGRAPH_CTX_CACHE(1, 0),
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NV10_PGRAPH_CTX_CACHE(1, 1),
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NV10_PGRAPH_CTX_CACHE(1, 2),
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NV10_PGRAPH_CTX_CACHE(1, 3),
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NV10_PGRAPH_CTX_CACHE(1, 4),
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NV10_PGRAPH_CTX_CACHE(2, 0),
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NV10_PGRAPH_CTX_CACHE(2, 1),
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NV10_PGRAPH_CTX_CACHE(2, 2),
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NV10_PGRAPH_CTX_CACHE(2, 3),
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NV10_PGRAPH_CTX_CACHE(2, 4),
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NV10_PGRAPH_CTX_CACHE(3, 0),
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NV10_PGRAPH_CTX_CACHE(3, 1),
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NV10_PGRAPH_CTX_CACHE(3, 2),
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NV10_PGRAPH_CTX_CACHE(3, 3),
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NV10_PGRAPH_CTX_CACHE(3, 4),
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NV10_PGRAPH_CTX_CACHE(4, 0),
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NV10_PGRAPH_CTX_CACHE(4, 1),
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NV10_PGRAPH_CTX_CACHE(4, 2),
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NV10_PGRAPH_CTX_CACHE(4, 3),
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NV10_PGRAPH_CTX_CACHE(4, 4),
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NV10_PGRAPH_CTX_CACHE(5, 0),
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NV10_PGRAPH_CTX_CACHE(5, 1),
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NV10_PGRAPH_CTX_CACHE(5, 2),
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NV10_PGRAPH_CTX_CACHE(5, 3),
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NV10_PGRAPH_CTX_CACHE(5, 4),
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NV10_PGRAPH_CTX_CACHE(6, 0),
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NV10_PGRAPH_CTX_CACHE(6, 1),
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NV10_PGRAPH_CTX_CACHE(6, 2),
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NV10_PGRAPH_CTX_CACHE(6, 3),
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NV10_PGRAPH_CTX_CACHE(6, 4),
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NV10_PGRAPH_CTX_CACHE(7, 0),
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NV10_PGRAPH_CTX_CACHE(7, 1),
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NV10_PGRAPH_CTX_CACHE(7, 2),
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NV10_PGRAPH_CTX_CACHE(7, 3),
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NV10_PGRAPH_CTX_CACHE(7, 4),
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NV10_PGRAPH_CTX_USER,
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NV04_PGRAPH_DMA_START_0,
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NV04_PGRAPH_DMA_START_1,
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@ -653,6 +653,78 @@ static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
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return -1;
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}
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static void nv10_graph_load_dma_vtxbuf(struct nouveau_channel *chan,
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uint32_t inst)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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uint32_t st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
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uint32_t ctx_user, ctx_switch[5];
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int i, subchan = -1;
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/* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
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* that cannot be restored via MMIO. Do it through the FIFO
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* instead.
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*/
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/* Look for a celsius object */
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for (i = 0; i < 8; i++) {
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int class = nv_rd32(dev, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
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if (class == 0x56 || class == 0x96 || class == 0x99) {
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subchan = i;
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break;
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}
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}
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if (subchan < 0 || !inst)
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return;
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/* Save the current ctx object */
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ctx_user = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
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for (i = 0; i < 5; i++)
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ctx_switch[i] = nv_rd32(dev, NV10_PGRAPH_CTX_SWITCH(i));
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/* Save the FIFO state */
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st2 = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2);
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st2_dl = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2_DL);
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st2_dh = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2_DH);
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fifo_ptr = nv_rd32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR);
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for (i = 0; i < ARRAY_SIZE(fifo); i++)
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fifo[i] = nv_rd32(dev, 0x4007a0 + 4 * i);
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/* Switch to the celsius subchannel */
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for (i = 0; i < 5; i++)
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(i),
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nv_rd32(dev, NV10_PGRAPH_CTX_CACHE(subchan, i)));
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nv_mask(dev, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
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/* Inject NV10TCL_DMA_VTXBUF */
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2,
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0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
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nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
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pgraph->fifo_access(dev, true);
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pgraph->fifo_access(dev, false);
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/* Restore the FIFO state */
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for (i = 0; i < ARRAY_SIZE(fifo); i++)
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nv_wr32(dev, 0x4007a0 + 4 * i, fifo[i]);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, st2);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
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nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
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/* Restore the current ctx object */
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for (i = 0; i < 5; i++)
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
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nv_wr32(dev, NV10_PGRAPH_CTX_USER, ctx_user);
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}
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int nv10_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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@ -670,6 +742,8 @@ int nv10_graph_load_context(struct nouveau_channel *chan)
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}
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nv10_graph_load_pipe(chan);
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nv10_graph_load_dma_vtxbuf(chan, (nv_rd32(dev, NV10_PGRAPH_GLOBALSTATE1)
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& 0xffff));
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
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@ -856,11 +930,12 @@ int nv10_graph_init(struct drm_device *dev)
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for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
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nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
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nv_wr32(dev, NV10_PGRAPH_STATE, 0xFFFFFFFF);
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tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
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