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drm/amdgpu: enable sw clock gating for vcn
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -501,7 +501,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
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vcn_v1_0_mc_resume(adev);
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/* disable clock gating */
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vcn_v1_0_disable_clock_gating(adev, false);
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vcn_v1_0_disable_clock_gating(adev, true);
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/* disable interupt */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
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@ -682,7 +682,7 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* enable clock gating */
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vcn_v1_0_enable_clock_gating(adev, false);
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vcn_v1_0_enable_clock_gating(adev, true);
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return 0;
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}
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