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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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MMC host:
- mtk-sd: Fix tuning for MT8173 HS200/HS400 mode - sdhci: Revert a fix for incorrect switch to HS mode - sdhci-msm: Fixup accesses to the DDR_CONFIG register - sdhci-of-esdhc: Revert a bad fix for erratum A-009204 - sdhci-of-esdhc: Re-implement fix for erratum A-009204 - sdhci-of-esdhc: Fixup P2020 errata handling - sdhci-pci: Disable broken CMDQ on Intel GLK based Lenovo systems -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAl38kp0XHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCka4g/+IgSL+kj4eaqIAKvEnTXAqSeC 9qpJQ5D4Aa3NvX4HrYZ9ks0vnxCjmcnWrXyANdbGwnKNkLlh2QevfS3+5EVnnJ/i UlMW71ohhdCsNYGSAookhVCemoKfYraq+GiHa2w6XKP1c80avX/13cL8L6tN0k/s ti36ia6GemTX0k/xp2X8lej/Kd4CCqSveS+jpUtvzB/6BJEDrSvrtCBW2EYDh5Od JejMXyTAERiNh9URsFetJQHAkyvGpsal0bd+cb3n5eDnJOSFkUCmCAMgN+lUxJbp eC7OFGFJEyKf/isjjIafWI91l/tsMSVSD5JMxN5WO6qMj8gnNA4Ky6jnq/e2cRiK nbbDuyYpRBGP70lEZtL8UwQPj166CtKxqpR2Re0poBirqRGI10NNnXNiSvtWQ14u UBY6ExrwZUu/EvJ1kW8oA5siB775WtJLtvze4h0seANHMPmDIZoHORJ3C/jCCgcm Hod6Jj7HZIHh3MTlreEm1gy02zroSepbvhPDf1oJL5G/iFmYlDh7cB++D8puvyY/ Pe6Lqeo+ZbDlZ5QOApIIrp2MfQmaeeN6rHpqBVcowlIt6tzq9NaIU8Rip7s6Z9Ph leHt/XSfSyGp1ijdY301MVP1HWsawYQfNh2LX+fYTMi31UmDXdu7iKWi/TBhHHmp RlhpIAY9SPuQ9d7ZE0I= =CJwr -----END PGP SIGNATURE----- Merge tag 'mmc-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC host fixes from Ulf Hansson: - mtk-sd: Fix tuning for MT8173 HS200/HS400 mode - sdhci: Revert a fix for incorrect switch to HS mode - sdhci-msm: Fixup accesses to the DDR_CONFIG register - sdhci-of-esdhc: Revert a bad fix for erratum A-009204 - sdhci-of-esdhc: Re-implement fix for erratum A-009204 - sdhci-of-esdhc: Fixup P2020 errata handling - sdhci-pci: Disable broken CMDQ on Intel GLK based Lenovo systems * tag 'mmc-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-of-esdhc: re-implement erratum A-009204 workaround mmc: sdhci: Add a quirk for broken command queuing mmc: sdhci: Workaround broken command queuing on Intel GLK mmc: sdhci-of-esdhc: fix P2020 errata handling mmc: sdhci: Update the tuning failed messages to pr_debug level mmc: sdhci-of-esdhc: Revert "mmc: sdhci-of-esdhc: add erratum A-009204 support" mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode mmc: sdhci-msm: Correct the offset and value for DDR_CONFIG register Revert "mmc: sdhci: Fix incorrect switch to HS mode"
This commit is contained in:
Linus Torvalds
commit
d2944d5313
@ -228,6 +228,7 @@
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#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
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#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
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#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
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#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
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#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
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@ -1881,6 +1882,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
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/* select EMMC50 PAD CMD tune */
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sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
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sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
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if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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mmc->ios.timing == MMC_TIMING_UHS_SDR104)
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@ -99,7 +99,7 @@
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#define CORE_PWRSAVE_DLL BIT(3)
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#define DDR_CONFIG_POR_VAL 0x80040853
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#define DDR_CONFIG_POR_VAL 0x80040873
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#define INVALID_TUNING_PHASE -1
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@ -148,8 +148,9 @@ struct sdhci_msm_offset {
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u32 core_ddr_200_cfg;
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u32 core_vendor_spec3;
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u32 core_dll_config_2;
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u32 core_dll_config_3;
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u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
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u32 core_ddr_config;
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u32 core_ddr_config_2;
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};
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static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
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@ -177,8 +178,8 @@ static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
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.core_ddr_200_cfg = 0x224,
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.core_vendor_spec3 = 0x250,
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.core_dll_config_2 = 0x254,
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.core_ddr_config = 0x258,
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.core_ddr_config_2 = 0x25c,
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.core_dll_config_3 = 0x258,
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.core_ddr_config = 0x25c,
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};
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static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
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@ -207,8 +208,8 @@ static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
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.core_ddr_200_cfg = 0x184,
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.core_vendor_spec3 = 0x1b0,
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.core_dll_config_2 = 0x1b4,
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.core_ddr_config = 0x1b8,
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.core_ddr_config_2 = 0x1bc,
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.core_ddr_config_old = 0x1b8,
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.core_ddr_config = 0x1bc,
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};
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struct sdhci_msm_variant_ops {
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@ -253,6 +254,7 @@ struct sdhci_msm_host {
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const struct sdhci_msm_offset *offset;
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bool use_cdr;
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u32 transfer_mode;
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bool updated_ddr_cfg;
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};
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static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
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@ -924,8 +926,10 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
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static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
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{
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struct mmc_host *mmc = host->mmc;
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u32 dll_status, config;
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u32 dll_status, config, ddr_cfg_offset;
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int ret;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_msm_offset *msm_offset =
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sdhci_priv_msm_offset(host);
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@ -938,8 +942,11 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
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* bootloaders. In the future, if this changes, then the desired
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* values will need to be programmed appropriately.
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*/
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writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
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msm_offset->core_ddr_config);
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if (msm_host->updated_ddr_cfg)
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ddr_cfg_offset = msm_offset->core_ddr_config;
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else
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ddr_cfg_offset = msm_offset->core_ddr_config_old;
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writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
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if (mmc->ios.enhanced_strobe) {
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config = readl_relaxed(host->ioaddr +
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@ -1899,6 +1906,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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msm_offset->core_vendor_spec_capabilities0);
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}
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if (core_major == 1 && core_minor >= 0x49)
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msm_host->updated_ddr_cfg = true;
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/*
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* Power on reset state may trigger power irq if previous status of
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* PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
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@ -80,6 +80,7 @@ struct sdhci_esdhc {
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bool quirk_tuning_erratum_type1;
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bool quirk_tuning_erratum_type2;
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bool quirk_ignore_data_inhibit;
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bool quirk_delay_before_data_reset;
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bool in_sw_tuning;
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unsigned int peripheral_clock;
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const struct esdhc_clk_fixup *clk_fixup;
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@ -759,14 +760,16 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
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struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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u32 val;
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if (esdhc->quirk_delay_before_data_reset &&
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(mask & SDHCI_RESET_DATA) &&
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(host->flags & SDHCI_REQ_USE_DMA))
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mdelay(5);
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sdhci_reset(host, mask);
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
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mdelay(5);
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if (mask & SDHCI_RESET_ALL) {
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val = sdhci_readl(host, ESDHC_TBCTL);
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val &= ~ESDHC_TB_EN;
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@ -1221,6 +1224,10 @@ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
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if (match)
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esdhc->clk_fixup = match->data;
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np = pdev->dev.of_node;
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if (of_device_is_compatible(np, "fsl,p2020-esdhc"))
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esdhc->quirk_delay_before_data_reset = true;
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clk = of_clk_get(np, 0);
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if (!IS_ERR(clk)) {
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/*
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@ -1303,8 +1310,8 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
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host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
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if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
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host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
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host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
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host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
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host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
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}
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if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
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@ -27,6 +27,7 @@
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#include <linux/mmc/slot-gpio.h>
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#include <linux/mmc/sdhci-pci-data.h>
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#ifdef CONFIG_X86
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#include <asm/iosf_mbi.h>
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@ -783,11 +784,18 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
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return 0;
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}
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static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
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{
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return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
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dmi_match(DMI_BIOS_VENDOR, "LENOVO");
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}
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static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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int ret = byt_emmc_probe_slot(slot);
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slot->host->mmc->caps2 |= MMC_CAP2_CQE;
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if (!glk_broken_cqhci(slot))
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slot->host->mmc->caps2 |= MMC_CAP2_CQE;
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if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
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slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
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@ -1882,9 +1882,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (timing == MMC_TIMING_UHS_SDR12)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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else if (timing == MMC_TIMING_SD_HS ||
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timing == MMC_TIMING_MMC_HS ||
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timing == MMC_TIMING_UHS_SDR25)
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else if (timing == MMC_TIMING_UHS_SDR25)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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@ -2419,8 +2417,8 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
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sdhci_send_tuning(host, opcode);
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if (!host->tuning_done) {
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pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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sdhci_abort_tuning(host, opcode);
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return -ETIMEDOUT;
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}
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@ -3769,6 +3767,9 @@ int sdhci_setup_host(struct sdhci_host *host)
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mmc_hostname(mmc), host->version);
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}
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if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
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mmc->caps2 &= ~MMC_CAP2_CQE;
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if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
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host->flags |= SDHCI_USE_SDMA;
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else if (!(host->caps & SDHCI_CAN_DO_SDMA))
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@ -409,6 +409,8 @@ struct sdhci_host {
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#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
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/* Controller reports inverted write-protect state */
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#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
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/* Controller has unusable command queue engine */
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#define SDHCI_QUIRK_BROKEN_CQE (1<<17)
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/* Controller does not like fast PIO transfers */
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#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
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/* Controller does not have a LED */
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