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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 08:30:54 +07:00
q40ide breakage
again, fallout from ide merge Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -36,23 +36,6 @@ static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
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PCIDE_BASE6 */
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};
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/*
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* Offsets from one of the above bases
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*/
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/* used to do addr translation here but it is easier to do in setup ports */
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/*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
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#define IDE_OFF_B(x) ((unsigned long)((IDE_##x##_OFFSET)))
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#define IDE_OFF_W(x) ((unsigned long)((IDE_##x##_OFFSET)))
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static const int pcide_offsets[IDE_NR_PORTS] = {
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IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
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IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
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518/*IDE_OFF(CMD)*/
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};
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static int q40ide_default_irq(unsigned long base)
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{
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switch (base) {
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@ -68,23 +51,22 @@ static int q40ide_default_irq(unsigned long base)
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/*
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* Addresses are pretranslated for Q40 ISA access.
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*/
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void q40_ide_setup_ports ( hw_regs_t *hw,
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unsigned long base, int *offsets,
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unsigned long ctrl, unsigned long intr,
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static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
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ide_ack_intr_t *ack_intr,
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int irq)
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{
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int i;
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memset(hw, 0, sizeof(hw_regs_t));
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for (i = 0; i < IDE_NR_PORTS; i++) {
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/* BIG FAT WARNING:
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assumption: only DATA port is ever used in 16 bit mode */
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if (i == 0)
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hw->io_ports_array[i] = Q40_ISA_IO_W(base + offsets[i]);
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else
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hw->io_ports_array[i] = Q40_ISA_IO_B(base + offsets[i]);
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}
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/* BIG FAT WARNING:
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assumption: only DATA port is ever used in 16 bit mode */
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hw->io_ports.data_addr = Q40_ISA_IO_W(base);
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hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
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hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
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hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
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hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
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hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
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hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
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hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
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hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
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hw->irq = irq;
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hw->ack_intr = ack_intr;
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@ -131,9 +113,8 @@ static int __init q40ide_init(void)
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release_region(pcide_bases[i], 8);
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continue;
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}
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q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets,
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pcide_bases[i]+0x206,
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0, NULL,
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q40_ide_setup_ports(&hw, pcide_bases[i],
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NULL,
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// m68kide_iops,
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q40ide_default_irq(pcide_bases[i]));
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