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drm/amdgpu/dce11: simplify hpd code

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use the hpd enum directly as an index

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-09-28 13:56:50 -04:00
parent 03ae23b93b
commit d2486d25bd
1 changed files with 15 additions and 99 deletions
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114
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
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@ -346,33 +346,12 @@ static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
enum amdgpu_hpd_id hpd) enum amdgpu_hpd_id hpd)
{ {
int idx;
bool connected = false; bool connected = false;
switch (hpd) { if (hpd >= adev->mode_info.num_hpd)
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
return connected; return connected;
}
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
connected = true; connected = true;
@ -392,37 +371,16 @@ static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
{ {
u32 tmp; u32 tmp;
bool connected = dce_v11_0_hpd_sense(adev, hpd); bool connected = dce_v11_0_hpd_sense(adev, hpd);
int idx;
switch (hpd) { if (hpd >= adev->mode_info.num_hpd)
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
return; return;
}
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
if (connected) if (connected)
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
else else
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
} }
/** /**
@ -438,33 +396,12 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
struct drm_device *dev = adev->ddev; struct drm_device *dev = adev->ddev;
struct drm_connector *connector; struct drm_connector *connector;
u32 tmp; u32 tmp;
int idx;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
switch (amdgpu_connector->hpd.hpd) { if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
continue; continue;
}
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
@ -473,24 +410,24 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
* https://bugzilla.redhat.com/show_bug.cgi?id=726143 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
* also avoid interrupt storms during dpms. * also avoid interrupt storms during dpms.
*/ */
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
continue; continue;
} }
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
DC_HPD_CONNECT_INT_DELAY, DC_HPD_CONNECT_INT_DELAY,
AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
DC_HPD_DISCONNECT_INT_DELAY, DC_HPD_DISCONNECT_INT_DELAY,
AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
@ -510,37 +447,16 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
struct drm_device *dev = adev->ddev; struct drm_device *dev = adev->ddev;
struct drm_connector *connector; struct drm_connector *connector;
u32 tmp; u32 tmp;
int idx;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
switch (amdgpu_connector->hpd.hpd) { if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
continue; continue;
}
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
} }