From d1b32c32e8943d18a104f347fbe40c46276011d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 13 May 2016 23:41:40 +0300 Subject: [PATCH] drm/i915: Set BXT cdclk to minimum initially MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In case the driver is initialized without active displays, we should just drop the cdclk to the minimum frequency right off the bat. There might not be a modeset to drop it to the minimum late rafter all. With DMC supposedly we should always have the cdclk up and running. The DMC will shut the DE PLL down when appropriate, so let's nuke the related FIXMEs as well. Trying to do anything different would go against the expectations of the DMC firmware, and we all know how fragile the DMC firmware is. Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-22-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d53b670328e4..fd171fd2b255 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -119,6 +119,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state); static void intel_modeset_verify_crtc(struct drm_crtc *crtc, struct drm_crtc_state *old_state, struct drm_crtc_state *new_state); +static int broxton_calc_cdclk(int max_pixclk); struct intel_limit { struct { @@ -5421,10 +5422,8 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv) * FIXME: * - The initial CDCLK needs to be read from VBT. * Need to make this change after VBT has changes for BXT. - * - check if setting the max (or any) cdclk freq is really necessary - * here, it belongs to modeset time */ - broxton_set_cdclk(dev_priv, 624000); + broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0)); } void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) @@ -5864,10 +5863,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, static int broxton_calc_cdclk(int max_pixclk) { - /* - * FIXME: - * - set 19.2MHz bypass frequency if there are no active pipes - */ if (max_pixclk > 576000) return 624000; else if (max_pixclk > 384000)