mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar: "Most of the commits are continued SGI UV4 hardware-enablement changes, plus there's also new Bluetooth support for the Intel Edison platform" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/platform/intel-mid: Enable Bluetooth support on Intel Edison x86/platform/uv/BAU: Implement uv4_wait_completion with read_status x86/platform/uv/BAU: Add wait_completion to bau_operations x86/platform/uv/BAU: Add status mmr location fields to bau_control x86/platform/uv/BAU: Cleanup bau_operations declaration and instances x86/platform/uv/BAU: Add payload descriptor qualifier x86/platform/uv/BAU: Add uv_bau_version enumerated constants
This commit is contained in:
Linus Torvalds
commit
d19458a4ea
@ -185,6 +185,15 @@
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#define MSG_REGULAR 1
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#define MSG_RETRY 2
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#define BAU_DESC_QUALIFIER 0x534749
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enum uv_bau_version {
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UV_BAU_V1 = 1,
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UV_BAU_V2,
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UV_BAU_V3,
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UV_BAU_V4,
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};
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/*
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* Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
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* If the 'multilevel' flag in the header portion of the descriptor
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@ -222,20 +231,32 @@ struct bau_local_cpumask {
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* the s/w ack bit vector ]
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*/
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/*
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* The payload is software-defined for INTD transactions
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/**
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* struct uv1_2_3_bau_msg_payload - defines payload for INTD transactions
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* @address: Signifies a page or all TLB's of the cpu
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* @sending_cpu: CPU from which the message originates
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* @acknowledge_count: CPUs on the destination Hub that received the interrupt
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*/
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struct bau_msg_payload {
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unsigned long address; /* signifies a page or all
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TLB's of the cpu */
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/* 64 bits */
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unsigned short sending_cpu; /* filled in by sender */
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/* 16 bits */
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unsigned short acknowledge_count; /* filled in by destination */
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/* 16 bits */
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unsigned int reserved1:32; /* not usable */
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struct uv1_2_3_bau_msg_payload {
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u64 address;
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u16 sending_cpu;
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u16 acknowledge_count;
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};
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/**
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* struct uv4_bau_msg_payload - defines payload for INTD transactions
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* @address: Signifies a page or all TLB's of the cpu
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* @sending_cpu: CPU from which the message originates
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* @acknowledge_count: CPUs on the destination Hub that received the interrupt
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* @qualifier: Set by source to verify origin of INTD broadcast
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*/
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struct uv4_bau_msg_payload {
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u64 address;
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u16 sending_cpu;
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u16 acknowledge_count;
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u32 reserved:8;
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u32 qualifier:24;
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};
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/*
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* UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
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@ -385,17 +406,6 @@ struct uv2_3_bau_msg_header {
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/* bits 127:120 */
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};
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/* Abstracted BAU functions */
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struct bau_operations {
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unsigned long (*read_l_sw_ack)(void);
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unsigned long (*read_g_sw_ack)(int pnode);
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unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
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void (*write_l_sw_ack)(unsigned long mmr);
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void (*write_g_sw_ack)(int pnode, unsigned long mmr);
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void (*write_payload_first)(int pnode, unsigned long mmr);
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void (*write_payload_last)(int pnode, unsigned long mmr);
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};
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/*
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* The activation descriptor:
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* The format of the message to send, plus all accompanying control
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@ -411,7 +421,10 @@ struct bau_desc {
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struct uv2_3_bau_msg_header uv2_3_hdr;
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} header;
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struct bau_msg_payload payload;
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union bau_payload_header {
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struct uv1_2_3_bau_msg_payload uv1_2_3;
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struct uv4_bau_msg_payload uv4;
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} payload;
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};
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/* UV1:
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* -payload-- ---------header------
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@ -588,8 +601,12 @@ struct uvhub_desc {
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struct socket_desc socket[2];
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};
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/*
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* one per-cpu; to locate the software tables
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/**
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* struct bau_control
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* @status_mmr: location of status mmr, determined by uvhub_cpu
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* @status_index: index of ERR|BUSY bits in status mmr, determined by uvhub_cpu
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*
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* Per-cpu control struct containing CPU topology information and BAU tuneables.
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*/
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struct bau_control {
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struct bau_desc *descriptor_base;
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@ -607,6 +624,8 @@ struct bau_control {
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int timeout_tries;
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int ipi_attempts;
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int conseccompletes;
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u64 status_mmr;
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int status_index;
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bool nobau;
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short baudisabled;
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short cpu;
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@ -644,6 +663,19 @@ struct bau_control {
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struct hub_and_pnode *thp;
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};
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/* Abstracted BAU functions */
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struct bau_operations {
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unsigned long (*read_l_sw_ack)(void);
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unsigned long (*read_g_sw_ack)(int pnode);
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unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
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void (*write_l_sw_ack)(unsigned long mmr);
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void (*write_g_sw_ack)(int pnode, unsigned long mmr);
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void (*write_payload_first)(int pnode, unsigned long mmr);
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void (*write_payload_last)(int pnode, unsigned long mmr);
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int (*wait_completion)(struct bau_desc*,
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struct bau_control*, long try);
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};
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static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
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{
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write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
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@ -2,8 +2,9 @@
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obj-$(subst m,y,$(CONFIG_PINCTRL_MERRIFIELD)) += platform_mrfld_pinctrl.o
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# SDHCI Devices
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obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += platform_mrfld_sd.o
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# WiFi
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# WiFi + BT
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obj-$(subst m,y,$(CONFIG_BRCMFMAC_SDIO)) += platform_bcm43xx.o
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obj-$(subst m,y,$(CONFIG_BT_HCIUART_BCM)) += platform_bt.o
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# IPC Devices
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obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic.o
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obj-$(subst m,y,$(CONFIG_SND_MFLD_MACHINE)) += platform_msic_audio.o
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108
arch/x86/platform/intel-mid/device_libs/platform_bt.c
Normal file
108
arch/x86/platform/intel-mid/device_libs/platform_bt.c
Normal file
@ -0,0 +1,108 @@
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/*
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* Bluetooth platform data initialization file
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*
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* (C) Copyright 2017 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/gpio/machine.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/intel-mid.h>
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struct bt_sfi_data {
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struct device *dev;
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const char *name;
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int (*setup)(struct bt_sfi_data *ddata);
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};
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static struct gpiod_lookup_table tng_bt_sfi_gpio_table = {
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.dev_id = "hci_bcm",
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.table = {
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GPIO_LOOKUP("0000:00:0c.0", -1, "device-wakeup", GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP("0000:00:0c.0", -1, "shutdown", GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP("0000:00:0c.0", -1, "host-wakeup", GPIO_ACTIVE_HIGH),
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{ },
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},
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};
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#define TNG_BT_SFI_GPIO_DEVICE_WAKEUP "bt_wakeup"
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#define TNG_BT_SFI_GPIO_SHUTDOWN "BT-reset"
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#define TNG_BT_SFI_GPIO_HOST_WAKEUP "bt_uart_enable"
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static int __init tng_bt_sfi_setup(struct bt_sfi_data *ddata)
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{
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struct gpiod_lookup_table *table = &tng_bt_sfi_gpio_table;
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struct gpiod_lookup *lookup = table->table;
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struct pci_dev *pdev;
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/* Connected to /dev/ttyS0 */
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pdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(4, 1));
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if (!pdev)
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return -ENODEV;
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ddata->dev = &pdev->dev;
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ddata->name = table->dev_id;
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lookup[0].chip_hwnum = get_gpio_by_name(TNG_BT_SFI_GPIO_DEVICE_WAKEUP);
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lookup[1].chip_hwnum = get_gpio_by_name(TNG_BT_SFI_GPIO_SHUTDOWN);
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lookup[2].chip_hwnum = get_gpio_by_name(TNG_BT_SFI_GPIO_HOST_WAKEUP);
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gpiod_add_lookup_table(table);
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return 0;
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}
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static struct bt_sfi_data tng_bt_sfi_data __initdata = {
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.setup = tng_bt_sfi_setup,
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};
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#define ICPU(model, ddata) \
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (kernel_ulong_t)&ddata }
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static const struct x86_cpu_id bt_sfi_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD, tng_bt_sfi_data),
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{}
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};
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static int __init bt_sfi_init(void)
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{
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struct platform_device_info info;
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struct platform_device *pdev;
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const struct x86_cpu_id *id;
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struct bt_sfi_data *ddata;
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int ret;
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id = x86_match_cpu(bt_sfi_cpu_ids);
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if (!id)
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return -ENODEV;
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ddata = (struct bt_sfi_data *)id->driver_data;
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if (!ddata)
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return -ENODEV;
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ret = ddata->setup(ddata);
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if (ret)
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return ret;
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memset(&info, 0, sizeof(info));
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info.fwnode = ddata->dev->fwnode;
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info.parent = ddata->dev;
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info.name = ddata->name,
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info.id = PLATFORM_DEVID_NONE,
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pdev = platform_device_register_full(&info);
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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dev_info(ddata->dev, "Registered Bluetooth device: %s\n", ddata->name);
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return 0;
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}
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device_initcall(bt_sfi_init);
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@ -23,28 +23,7 @@
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#include <asm/irq_vectors.h>
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#include <asm/timer.h>
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static struct bau_operations ops;
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static struct bau_operations uv123_bau_ops = {
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.bau_gpa_to_offset = uv_gpa_to_offset,
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.read_l_sw_ack = read_mmr_sw_ack,
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.read_g_sw_ack = read_gmmr_sw_ack,
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.write_l_sw_ack = write_mmr_sw_ack,
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.write_g_sw_ack = write_gmmr_sw_ack,
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.write_payload_first = write_mmr_payload_first,
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.write_payload_last = write_mmr_payload_last,
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};
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static struct bau_operations uv4_bau_ops = {
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.bau_gpa_to_offset = uv_gpa_to_soc_phys_ram,
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.read_l_sw_ack = read_mmr_proc_sw_ack,
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.read_g_sw_ack = read_gmmr_proc_sw_ack,
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.write_l_sw_ack = write_mmr_proc_sw_ack,
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.write_g_sw_ack = write_gmmr_proc_sw_ack,
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.write_payload_first = write_mmr_proc_payload_first,
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.write_payload_last = write_mmr_proc_payload_last,
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};
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static struct bau_operations ops __ro_after_init;
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/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
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static int timeout_base_ns[] = {
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@ -548,11 +527,12 @@ static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
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* return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
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*/
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static int uv1_wait_completion(struct bau_desc *bau_desc,
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unsigned long mmr_offset, int right_shift,
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struct bau_control *bcp, long try)
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{
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unsigned long descriptor_status;
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cycles_t ttm;
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u64 mmr_offset = bcp->status_mmr;
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int right_shift = bcp->status_index;
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struct ptc_stats *stat = bcp->statp;
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descriptor_status = uv1_read_status(mmr_offset, right_shift);
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@ -640,11 +620,12 @@ int handle_uv2_busy(struct bau_control *bcp)
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}
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static int uv2_3_wait_completion(struct bau_desc *bau_desc,
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unsigned long mmr_offset, int right_shift,
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struct bau_control *bcp, long try)
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{
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unsigned long descriptor_stat;
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cycles_t ttm;
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u64 mmr_offset = bcp->status_mmr;
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int right_shift = bcp->status_index;
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int desc = bcp->uvhub_cpu;
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long busy_reps = 0;
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struct ptc_stats *stat = bcp->statp;
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@ -706,28 +687,59 @@ static int uv2_3_wait_completion(struct bau_desc *bau_desc,
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}
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/*
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* There are 2 status registers; each and array[32] of 2 bits. Set up for
|
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* which register to read and position in that register based on cpu in
|
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* current hub.
|
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* Returns the status of current BAU message for cpu desc as a bit field
|
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* [Error][Busy][Aux]
|
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*/
|
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static int wait_completion(struct bau_desc *bau_desc, struct bau_control *bcp, long try)
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static u64 read_status(u64 status_mmr, int index, int desc)
|
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{
|
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int right_shift;
|
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unsigned long mmr_offset;
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u64 stat;
|
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stat = ((read_lmmr(status_mmr) >> index) & UV_ACT_STATUS_MASK) << 1;
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stat |= (read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_2) >> desc) & 0x1;
|
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|
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return stat;
|
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}
|
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|
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static int uv4_wait_completion(struct bau_desc *bau_desc,
|
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struct bau_control *bcp, long try)
|
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{
|
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struct ptc_stats *stat = bcp->statp;
|
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u64 descriptor_stat;
|
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u64 mmr = bcp->status_mmr;
|
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int index = bcp->status_index;
|
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int desc = bcp->uvhub_cpu;
|
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|
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if (desc < UV_CPUS_PER_AS) {
|
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mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
|
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right_shift = desc * UV_ACT_STATUS_SIZE;
|
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} else {
|
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mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
|
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right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
|
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}
|
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descriptor_stat = read_status(mmr, index, desc);
|
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|
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if (bcp->uvhub_version == 1)
|
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return uv1_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
|
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else
|
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return uv2_3_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
|
||||
/* spin on the status MMR, waiting for it to go idle */
|
||||
while (descriptor_stat != UV2H_DESC_IDLE) {
|
||||
switch (descriptor_stat) {
|
||||
case UV2H_DESC_SOURCE_TIMEOUT:
|
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stat->s_stimeout++;
|
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return FLUSH_GIVEUP;
|
||||
|
||||
case UV2H_DESC_DEST_TIMEOUT:
|
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stat->s_dtimeout++;
|
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bcp->conseccompletes = 0;
|
||||
return FLUSH_RETRY_TIMEOUT;
|
||||
|
||||
case UV2H_DESC_DEST_STRONG_NACK:
|
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stat->s_plugged++;
|
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bcp->conseccompletes = 0;
|
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return FLUSH_RETRY_PLUGGED;
|
||||
|
||||
case UV2H_DESC_DEST_PUT_ERR:
|
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bcp->conseccompletes = 0;
|
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return FLUSH_GIVEUP;
|
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|
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default:
|
||||
/* descriptor_stat is still BUSY */
|
||||
cpu_relax();
|
||||
}
|
||||
descriptor_stat = read_status(mmr, index, desc);
|
||||
}
|
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bcp->conseccompletes++;
|
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return FLUSH_COMPLETE;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -918,7 +930,7 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
|
||||
struct uv1_bau_msg_header *uv1_hdr = NULL;
|
||||
struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
|
||||
|
||||
if (bcp->uvhub_version == 1) {
|
||||
if (bcp->uvhub_version == UV_BAU_V1) {
|
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uv1 = 1;
|
||||
uv1_throttle(hmaster, stat);
|
||||
}
|
||||
@ -958,7 +970,7 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
|
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write_mmr_activation(index);
|
||||
|
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try++;
|
||||
completion_stat = wait_completion(bau_desc, bcp, try);
|
||||
completion_stat = ops.wait_completion(bau_desc, bcp, try);
|
||||
|
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handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
|
||||
|
||||
@ -1114,15 +1126,12 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
|
||||
unsigned long end,
|
||||
unsigned int cpu)
|
||||
{
|
||||
int locals = 0;
|
||||
int remotes = 0;
|
||||
int hubs = 0;
|
||||
int locals = 0, remotes = 0, hubs = 0;
|
||||
struct bau_desc *bau_desc;
|
||||
struct cpumask *flush_mask;
|
||||
struct ptc_stats *stat;
|
||||
struct bau_control *bcp;
|
||||
unsigned long descriptor_status;
|
||||
unsigned long status;
|
||||
unsigned long descriptor_status, status, address;
|
||||
|
||||
bcp = &per_cpu(bau_control, cpu);
|
||||
|
||||
@ -1171,10 +1180,24 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
|
||||
record_send_statistics(stat, locals, hubs, remotes, bau_desc);
|
||||
|
||||
if (!end || (end - start) <= PAGE_SIZE)
|
||||
bau_desc->payload.address = start;
|
||||
address = start;
|
||||
else
|
||||
bau_desc->payload.address = TLB_FLUSH_ALL;
|
||||
bau_desc->payload.sending_cpu = cpu;
|
||||
address = TLB_FLUSH_ALL;
|
||||
|
||||
switch (bcp->uvhub_version) {
|
||||
case UV_BAU_V1:
|
||||
case UV_BAU_V2:
|
||||
case UV_BAU_V3:
|
||||
bau_desc->payload.uv1_2_3.address = address;
|
||||
bau_desc->payload.uv1_2_3.sending_cpu = cpu;
|
||||
break;
|
||||
case UV_BAU_V4:
|
||||
bau_desc->payload.uv4.address = address;
|
||||
bau_desc->payload.uv4.sending_cpu = cpu;
|
||||
bau_desc->payload.uv4.qualifier = BAU_DESC_QUALIFIER;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* uv_flush_send_and_wait returns 0 if all cpu's were messaged,
|
||||
* or 1 if it gave up and the original cpumask should be returned.
|
||||
@ -1296,7 +1319,7 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
|
||||
|
||||
msgdesc.msg_slot = msg - msgdesc.queue_first;
|
||||
msgdesc.msg = msg;
|
||||
if (bcp->uvhub_version == 2)
|
||||
if (bcp->uvhub_version == UV_BAU_V2)
|
||||
process_uv2_message(&msgdesc, bcp);
|
||||
else
|
||||
/* no error workaround for uv1 or uv3 */
|
||||
@ -1838,7 +1861,7 @@ static void pq_init(int node, int pnode)
|
||||
* and the payload queue tail must be maintained by the kernel.
|
||||
*/
|
||||
bcp = &per_cpu(bau_control, smp_processor_id());
|
||||
if (bcp->uvhub_version <= 3) {
|
||||
if (bcp->uvhub_version <= UV_BAU_V3) {
|
||||
tail = first;
|
||||
gnode = uv_gpa_to_gnode(uv_gpa(pqp));
|
||||
first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail;
|
||||
@ -2034,8 +2057,7 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
|
||||
struct bau_control **smasterp,
|
||||
struct bau_control **hmasterp)
|
||||
{
|
||||
int i;
|
||||
int cpu;
|
||||
int i, cpu, uvhub_cpu;
|
||||
struct bau_control *bcp;
|
||||
|
||||
for (i = 0; i < sdp->num_cpus; i++) {
|
||||
@ -2052,19 +2074,33 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
|
||||
bcp->socket_master = *smasterp;
|
||||
bcp->uvhub = bdp->uvhub;
|
||||
if (is_uv1_hub())
|
||||
bcp->uvhub_version = 1;
|
||||
bcp->uvhub_version = UV_BAU_V1;
|
||||
else if (is_uv2_hub())
|
||||
bcp->uvhub_version = 2;
|
||||
bcp->uvhub_version = UV_BAU_V2;
|
||||
else if (is_uv3_hub())
|
||||
bcp->uvhub_version = 3;
|
||||
bcp->uvhub_version = UV_BAU_V3;
|
||||
else if (is_uv4_hub())
|
||||
bcp->uvhub_version = 4;
|
||||
bcp->uvhub_version = UV_BAU_V4;
|
||||
else {
|
||||
pr_emerg("uvhub version not 1, 2, 3, or 4\n");
|
||||
return 1;
|
||||
}
|
||||
bcp->uvhub_master = *hmasterp;
|
||||
bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu);
|
||||
uvhub_cpu = uv_cpu_blade_processor_id(cpu);
|
||||
bcp->uvhub_cpu = uvhub_cpu;
|
||||
|
||||
/*
|
||||
* The ERROR and BUSY status registers are located pairwise over
|
||||
* the STATUS_0 and STATUS_1 mmrs; each an array[32] of 2 bits.
|
||||
*/
|
||||
if (uvhub_cpu < UV_CPUS_PER_AS) {
|
||||
bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
|
||||
bcp->status_index = uvhub_cpu * UV_ACT_STATUS_SIZE;
|
||||
} else {
|
||||
bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
|
||||
bcp->status_index = (uvhub_cpu - UV_CPUS_PER_AS)
|
||||
* UV_ACT_STATUS_SIZE;
|
||||
}
|
||||
|
||||
if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
|
||||
pr_emerg("%d cpus per uvhub invalid\n",
|
||||
@ -2147,6 +2183,39 @@ static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct bau_operations uv1_bau_ops __initconst = {
|
||||
.bau_gpa_to_offset = uv_gpa_to_offset,
|
||||
.read_l_sw_ack = read_mmr_sw_ack,
|
||||
.read_g_sw_ack = read_gmmr_sw_ack,
|
||||
.write_l_sw_ack = write_mmr_sw_ack,
|
||||
.write_g_sw_ack = write_gmmr_sw_ack,
|
||||
.write_payload_first = write_mmr_payload_first,
|
||||
.write_payload_last = write_mmr_payload_last,
|
||||
.wait_completion = uv1_wait_completion,
|
||||
};
|
||||
|
||||
static const struct bau_operations uv2_3_bau_ops __initconst = {
|
||||
.bau_gpa_to_offset = uv_gpa_to_offset,
|
||||
.read_l_sw_ack = read_mmr_sw_ack,
|
||||
.read_g_sw_ack = read_gmmr_sw_ack,
|
||||
.write_l_sw_ack = write_mmr_sw_ack,
|
||||
.write_g_sw_ack = write_gmmr_sw_ack,
|
||||
.write_payload_first = write_mmr_payload_first,
|
||||
.write_payload_last = write_mmr_payload_last,
|
||||
.wait_completion = uv2_3_wait_completion,
|
||||
};
|
||||
|
||||
static const struct bau_operations uv4_bau_ops __initconst = {
|
||||
.bau_gpa_to_offset = uv_gpa_to_soc_phys_ram,
|
||||
.read_l_sw_ack = read_mmr_proc_sw_ack,
|
||||
.read_g_sw_ack = read_gmmr_proc_sw_ack,
|
||||
.write_l_sw_ack = write_mmr_proc_sw_ack,
|
||||
.write_g_sw_ack = write_gmmr_proc_sw_ack,
|
||||
.write_payload_first = write_mmr_proc_payload_first,
|
||||
.write_payload_last = write_mmr_proc_payload_last,
|
||||
.wait_completion = uv4_wait_completion,
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialization of BAU-related structures
|
||||
*/
|
||||
@ -2166,11 +2235,11 @@ static int __init uv_bau_init(void)
|
||||
if (is_uv4_hub())
|
||||
ops = uv4_bau_ops;
|
||||
else if (is_uv3_hub())
|
||||
ops = uv123_bau_ops;
|
||||
ops = uv2_3_bau_ops;
|
||||
else if (is_uv2_hub())
|
||||
ops = uv123_bau_ops;
|
||||
ops = uv2_3_bau_ops;
|
||||
else if (is_uv1_hub())
|
||||
ops = uv123_bau_ops;
|
||||
ops = uv1_bau_ops;
|
||||
|
||||
for_each_possible_cpu(cur_cpu) {
|
||||
mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user