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drm/i915: Leave DPLL ref clocks on

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We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-06-28 02:03:59 +03:00 committed by Daniel Vetter
parent d49a340d6e
commit d17ec4ced6
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_display.c
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@ -1684,7 +1684,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
assert_pipe_disabled(dev_priv, pipe); assert_pipe_disabled(dev_priv, pipe);
/* Set PLL en = 0 */ /* Set PLL en = 0 */
val = DPLL_SSC_REF_CLOCK_CHV; val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
if (pipe != PIPE_A) if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV; val |= DPLL_INTEGRATED_CRI_CLK_VLV;
I915_WRITE(DPLL(pipe), val); I915_WRITE(DPLL(pipe), val);