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drm/amd/pp: Change pstate_clk frequency unit to 10KHz on Rv

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to keep consistent with other asics

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-04-20 12:57:10 +08:00 committed by Alex Deucher
parent 4e418c3401
commit d10fb4a6f3
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
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@ -479,8 +479,8 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK; hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK; hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
return result; return result;
} }