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brcm80211: use native PCI register offsets
Signed-off-by: Stanislav Fomichev <kernel@fomichev.me> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -17,6 +17,8 @@
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#ifndef _h_pcicfg_
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#ifndef _h_pcicfg_
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#define _h_pcicfg_
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#define _h_pcicfg_
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#include <linux/pci_regs.h>
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/* The actual config space */
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/* The actual config space */
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#define PCI_BAR_MAX 6
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#define PCI_BAR_MAX 6
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@ -56,38 +58,6 @@ typedef struct _pci_config_regs {
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#define SZPCR (sizeof (pci_config_regs))
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#define SZPCR (sizeof (pci_config_regs))
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#define MINSZPCR 64 /* offsetof (dev_dep[0] */
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#define MINSZPCR 64 /* offsetof (dev_dep[0] */
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/* A structure for the config registers is nice, but in most
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* systems the config space is not memory mapped, so we need
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* field offsetts. :-(
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*/
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#define PCI_CFG_VID 0
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#define PCI_CFG_DID 2
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#define PCI_CFG_CMD 4
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#define PCI_CFG_STAT 6
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#define PCI_CFG_REV 8
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#define PCI_CFG_PROGIF 9
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#define PCI_CFG_SUBCL 0xa
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#define PCI_CFG_BASECL 0xb
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#define PCI_CFG_CLSZ 0xc
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#define PCI_CFG_LATTIM 0xd
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#define PCI_CFG_HDR 0xe
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#define PCI_CFG_BIST 0xf
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#define PCI_CFG_BAR0 0x10
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#define PCI_CFG_BAR1 0x14
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#define PCI_CFG_BAR2 0x18
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#define PCI_CFG_BAR3 0x1c
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#define PCI_CFG_BAR4 0x20
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#define PCI_CFG_BAR5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SVID 0x2c
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#define PCI_CFG_SSID 0x2e
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#define PCI_CFG_ROMBAR 0x30
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#define PCI_CFG_CAPPTR 0x34
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#define PCI_CFG_INT 0x3c
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#define PCI_CFG_PIN 0x3d
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#define PCI_CFG_MINGNT 0x3e
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#define PCI_CFG_MAXLAT 0x3f
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/* Classes and subclasses */
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/* Classes and subclasses */
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/* Header types */
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/* Header types */
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@ -130,16 +130,16 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
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u8 byte_val;
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u8 byte_val;
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/* check for Header type 0 */
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/* check for Header type 0 */
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pci_read_config_byte(dev, PCI_CFG_HDR, &byte_val);
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
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if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
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if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
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goto end;
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goto end;
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/* check if the capability pointer field exists */
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/* check if the capability pointer field exists */
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pci_read_config_byte(dev, PCI_CFG_STAT, &byte_val);
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pci_read_config_byte(dev, PCI_STATUS, &byte_val);
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if (!(byte_val & PCI_CAPPTR_PRESENT))
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if (!(byte_val & PCI_CAPPTR_PRESENT))
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goto end;
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goto end;
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pci_read_config_byte(dev, PCI_CFG_CAPPTR, &cap_ptr);
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pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
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/* check if the capability pointer is 0x00 */
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/* check if the capability pointer is 0x00 */
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if (cap_ptr == 0x00)
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if (cap_ptr == 0x00)
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goto end;
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goto end;
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@ -312,7 +312,8 @@ static __used void si_nvram_process(si_info_t *sii, char *pvars)
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switch (sii->pub.bustype) {
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switch (sii->pub.bustype) {
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case PCI_BUS:
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case PCI_BUS:
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/* do a pci config read to get subsystem id and subvendor id */
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/* do a pci config read to get subsystem id and subvendor id */
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pci_read_config_dword(sii->pbus, PCI_CFG_SVID, &w);
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pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID,
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&w);
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/* Let nvram variables override subsystem Vend/ID */
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/* Let nvram variables override subsystem Vend/ID */
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sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
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sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
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"boardvendor");
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"boardvendor");
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@ -1864,7 +1865,7 @@ bool si_deviceremoved(si_t *sih)
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switch (sih->bustype) {
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switch (sih->bustype) {
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case PCI_BUS:
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case PCI_BUS:
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ASSERT(sii->pbus != NULL);
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ASSERT(sii->pbus != NULL);
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pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w);
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pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
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if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
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if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
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return true;
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return true;
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break;
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break;
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