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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 21:16:40 +07:00
ARM: l2c: remove obsolete l2x0 ops for non-OF init
non-OF initialisation has never been used with any cache controller which isn't an ARM cache controller, so we can safely get rid of the old (and buggy) l2x0_*-based operations structure. This is also the last reference to: - l2x0_clean_line() - l2x0_inv_line() - l2x0_flush_line() - l2x0_flush_all() - l2x0_clean_all() - l2x0_inv_all() - l2x0_inv_range() - l2x0_clean_range() - l2x0_flush_range() - l2x0_enable() - l2x0_resume() so kill those functions too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
9081114837
commit
cf9ea8f130
@ -134,20 +134,6 @@ static inline void cache_sync(void)
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
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static inline void debug_writel(unsigned long val)
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{
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@ -161,27 +147,6 @@ static inline void debug_writel(unsigned long val)
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}
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#endif
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#ifdef CONFIG_PL310_ERRATA_588369
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#else
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
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}
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#endif
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static void l2x0_cache_sync(void)
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{
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unsigned long flags;
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@ -209,131 +174,6 @@ static void l2x0_flush_all(void)
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_all(void)
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{
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unsigned long flags;
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/* clean all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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__l2c_op_way(l2x0_base + L2X0_CLEAN_WAY);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_all(void)
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{
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unsigned long flags;
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/* invalidate all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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/* Invalidating when L2 is enabled is a nono */
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BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
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__l2c_op_way(l2x0_base + L2X0_INV_WAY);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(start);
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debug_writel(0x00);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(end);
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debug_writel(0x00);
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}
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_inv_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_clean_all();
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_clean_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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unsigned long flags;
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if ((end - start) >= l2x0_size) {
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l2x0_flush_all();
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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debug_writel(0x03);
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while (start < blk_end) {
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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debug_writel(0x00);
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_disable(void)
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{
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unsigned long flags;
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@ -345,49 +185,6 @@ static void l2x0_disable(void)
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock)
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{
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unsigned id;
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id = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK;
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if (id == L2X0_CACHE_ID_PART_L310)
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num_lock = 8;
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else
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num_lock = 1;
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/* l2x0 controller is disabled */
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writel_relaxed(aux, base + L2X0_AUX_CTRL);
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/* Make sure that I&D is not locked down when starting */
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l2c_unlock(base, num_lock);
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l2x0_inv_all();
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/* enable L2X0 */
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writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL);
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}
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static void l2x0_resume(void)
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{
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void __iomem *base = l2x0_base;
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if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
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l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0);
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}
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static const struct l2c_init_data l2x0_init_fns __initconst = {
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.enable = l2x0_enable,
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.outer_cache = {
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.inv_range = l2x0_inv_range,
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.clean_range = l2x0_clean_range,
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.flush_range = l2x0_flush_range,
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.flush_all = l2x0_flush_all,
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.disable = l2x0_disable,
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.sync = l2x0_cache_sync,
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.resume = l2x0_resume,
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},
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};
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/*
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* L2C-210 specific code.
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*
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@ -966,9 +763,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
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switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
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default:
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data = &l2x0_init_fns;
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break;
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case L2X0_CACHE_ID_PART_L210:
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data = &l2c210_data;
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break;
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