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PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs

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tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs.  However, part of tegra_pcie_phy_enable() needs to happen in all
cases.  Move that code up one level into tegra_pcie_phy_power_on().

[bhelgaas: changelog]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Stephen Warren 2016-07-25 16:02:21 -05:00 committed by Bjorn Helgaas
parent 08203f1fac
commit cf5d318012
1 changed files with 9 additions and 6 deletions
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15
drivers/pci/host/pci-tegra.c
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@ -838,12 +838,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
value |= PADS_PLL_CTL_RST_B4SM;
pads_writel(pcie, value, soc->pads_pll_ctl);
/* Configure the reference clock driver */
value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
pads_writel(pcie, value, PADS_REFCLK_CFG0);
if (soc->num_ports > 2)
pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
/* wait for the PLL to lock */
err = tegra_pcie_pll_wait(pcie, 500);
if (err < 0) {
@ -927,7 +921,9 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
{
const struct tegra_pcie_soc_data *soc = pcie->soc_data;
struct tegra_pcie_port *port;
u32 value;
int err;
if (pcie->legacy_phy) {
@ -952,6 +948,13 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
}
}
/* Configure the reference clock driver */
value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
pads_writel(pcie, value, PADS_REFCLK_CFG0);
if (soc->num_ports > 2)
pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
return 0;
}