AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-11 20:36:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

irqchip updates for 4.14-rc2

Browse Source 
- A GICv3 initialisation fix when some CPUs fail to be brought up
 - A GICv4 compile fix for GCC 4.5 (!)
 - A MIPS-GIC fix for the PCIe support
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlnBZkIVHG1hcmMuenlu
 Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDf2gP/R9+UB0qtNKlaqR82MkBIBSNSYir
 MRuKwei5++R6OKwHF7wGQxGLNhEOk2yTkZHn74JMdwXg3Y5s9puLzs3mlkFU2X6k
 2hM2oOrvjZTV4CNm6WwYzv15CAMVri9ETTAwXKg3KDHMvuMGhTgKef1TIyHHTHvP
 QhrmTW2k84uf+SYLOK3NPowWoNBrUUfO0fASgLLqmmLi2xnUeRR+a48CPuo9dS65
 n72zHoJjCyikLLsFbAmNuvEs4MDrDWJt9qF6VpVE0El5cOBqXuatz981i1STcD/U
 qJA5qUAZum9OVpIjpLO9lmZEdpW9gA+LHpyojrkqkBbhur2hYprLzIMUxCLSrqaq
 /jjW2Qdz7HY7QXBFLOEba3sfPJrp0hR7cNr0uuqaASHZDTEwScDl7ng05Iv8xRWD
 STCo2uXRx0WPBAnshtKHlSe7b9giheyoS7KZ0ONbpos+2AKVc6CcfIIutLouavPU
 Wg+IOUUxipkUyRCyLzsX+O8cabgrPgDHCC4CRJStTKVy5125okcDimZm/ybQsH7T
 1FrXnhTbUf3FWiSnXxj0N6hC7nydm1AtYh41Q4TlyAECLVKjDzKK2O9mekUlvb/d
 6iCg3xYzwbXhJLrG/kAgV64kO3/Dp/YyXXeRj+BVsU+SUkbEe5H6w5Imzd91mh8y
 JMAHGuEnDWLPryP+
 =lOJa
 -----END PGP SIGNATURE-----

Merge tag 'irqchip-4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip updates from Marc Zyngier

- A GICv3 initialisation fix when some CPUs fail to be brought up
- A GICv4 compile fix for GCC 4.5 (!)
- A MIPS-GIC fix for the PCIe support
This commit is contained in:
Thomas Gleixner 2017-09-21 11:57:08 +02:00
commit cf00ab842e
3 changed files with 16 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/irqchip/irq-gic-v3.c
View File

@ -1042,7 +1042,7 @@ static int get_cpu_number(struct device_node *dn)
{
const __be32 *cell;
u64 hwid;
int i;
int cpu;
cell = of_get_property(dn, "reg", NULL);
if (!cell)
@ -1056,9 +1056,9 @@ static int get_cpu_number(struct device_node *dn)
if (hwid & ~MPIDR_HWID_BITMASK)
return -1;
for (i = 0; i < num_possible_cpus(); i++)
if (cpu_logical_map(i) == hwid)
return i;
for_each_possible_cpu(cpu)
if (cpu_logical_map(cpu) == hwid)
return cpu;
return -1;
}

12
drivers/irqchip/irq-gic-v4.c
View File

@ -173,7 +173,9 @@ int its_map_vlpi(int irq, struct its_vlpi_map *map)
{
struct its_cmd_info info = {
.cmd_type = MAP_VLPI,
.map = map,
{
.map = map,
},
};
/*
@ -189,7 +191,9 @@ int its_get_vlpi(int irq, struct its_vlpi_map *map)
{
struct its_cmd_info info = {
.cmd_type = GET_VLPI,
.map = map,
{
.map = map,
},
};
return irq_set_vcpu_affinity(irq, &info);
@ -205,7 +209,9 @@ int its_prop_update_vlpi(int irq, u8 config, bool inv)
{
struct its_cmd_info info = {
.cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
.config = config,
{
.config = config,
},
};
return irq_set_vcpu_affinity(irq, &info);

6
drivers/irqchip/irq-mips-gic.c
View File

@ -169,7 +169,7 @@ static void gic_mask_irq(struct irq_data *d)
{
unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
write_gic_rmask(BIT(intr));
write_gic_rmask(intr);
gic_clear_pcpu_masks(intr);
}
@ -179,7 +179,7 @@ static void gic_unmask_irq(struct irq_data *d)
unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
unsigned int cpu;
write_gic_smask(BIT(intr));
write_gic_smask(intr);
gic_clear_pcpu_masks(intr);
cpu = cpumask_first_and(affinity, cpu_online_mask);
@ -767,7 +767,7 @@ static int __init gic_of_init(struct device_node *node,
for (i = 0; i < gic_shared_intrs; i++) {
change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
change_gic_trig(i, GIC_TRIG_LEVEL);
write_gic_rmask(BIT(i));
write_gic_rmask(i);
}
for (i = 0; i < gic_vpes; i++) {