AuxXxilium/linux_dsm_epyc7002
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Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next

Browse Source 
- Add SDIO gate to aspeed driver
 - Support aspeed AST2600 SoC
 - Add missing of_node_put() calls in various clk drivers
 - Drop NULL checks in clk debugfs
 - Add min/max rates to clk debugfs

* clk-aspeed:
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate

* clk-unused:
  clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
  clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
  clk: composite: Drop unused clk.h include
  clk: Si5341/Si5340: remove redundant assignment to n_den
  clk: qoriq: Fix -Wunused-const-variable

* clk-of-node-put:
  clk: ti: dm814x: Add of_node_put() to prevent memory leak
  clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
  clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
  clk: versatile: Add of_node_put() in cm_osc_setup()

* clk-const-bulk-data:
  clk: Constify struct clk_bulk_data * where possible

* clk-debugfs:
  clk: Drop !clk checks in debugfs dumping
  clk: Use seq_puts() in possible_parent_show()
  clk: Assert prepare_lock in clk_core_get_boundaries
  clk: Add clk_min/max_rate entries in debugfs
This commit is contained in:
Stephen Boyd 2019-09-19 15:30:40 -07:00
commit cee99529ee
11 changed files with 60 additions and 41 deletions
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1
drivers/clk/clk-composite.c
View File

@ -3,7 +3,6 @@
* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>

2
drivers/clk/clk-qoriq.c
View File

@ -686,7 +686,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
.guts_compat = "fsl,qoriq-device-config-1.0",
.init_periph = p5020_init_periph,
.cmux_groups = {
&p2041_cmux_grp1, &p2041_cmux_grp2
&p5020_cmux_grp1, &p5020_cmux_grp2
},
.cmux_to_group = {
0, 1, -1

1
drivers/clk/clk-si5341.c
View File

@ -547,7 +547,6 @@ static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
bool is_integer;
n_num = synth->data->freq_vco;
n_den = rate;
/* see if there's an integer solution */
r = do_div(n_num, rate);

58
drivers/clk/clk.c
View File

@ -593,6 +593,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
{
struct clk *clk_user;
lockdep_assert_held(&prepare_lock);
*min_rate = core->min_rate;
*max_rate = core->max_rate;
@ -2847,9 +2849,6 @@ static struct hlist_head *orphan_list[] = {
static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
int level)
{
if (!c)
return;
seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
level * 3 + 1, "",
30 - level * 3, c->name,
@ -2864,9 +2863,6 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
{
struct clk_core *child;
if (!c)
return;
clk_summary_show_one(s, c, level);
hlist_for_each_entry(child, &c->children, child_node)
@ -2896,8 +2892,9 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
{
if (!c)
return;
unsigned long min_rate, max_rate;
clk_core_get_boundaries(c, &min_rate, &max_rate);
/* This should be JSON format, i.e. elements separated with a comma */
seq_printf(s, "\"%s\": { ", c->name);
@ -2905,6 +2902,8 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
seq_printf(s, "\"protect_count\": %d,", c->protect_count);
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
seq_printf(s, "\"min_rate\": %lu,", min_rate);
seq_printf(s, "\"max_rate\": %lu,", max_rate);
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
seq_printf(s, "\"duty_cycle\": %u",
@ -2915,9 +2914,6 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
{
struct clk_core *child;
if (!c)
return;
clk_dump_one(s, c, level);
hlist_for_each_entry(child, &c->children, child_node) {
@ -3013,15 +3009,15 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
*/
parent = clk_core_get_parent_by_index(core, i);
if (parent)
seq_printf(s, "%s", parent->name);
seq_puts(s, parent->name);
else if (core->parents[i].name)
seq_printf(s, "%s", core->parents[i].name);
seq_puts(s, core->parents[i].name);
else if (core->parents[i].fw_name)
seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
else if (core->parents[i].index >= 0)
seq_printf(s, "%s",
of_clk_get_parent_name(core->of_node,
core->parents[i].index));
seq_puts(s,
of_clk_get_parent_name(core->of_node,
core->parents[i].index));
else
seq_puts(s, "(missing)");
@ -3064,6 +3060,34 @@ static int clk_duty_cycle_show(struct seq_file *s, void *data)
}
DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
static int clk_min_rate_show(struct seq_file *s, void *data)
{
struct clk_core *core = s->private;
unsigned long min_rate, max_rate;
clk_prepare_lock();
clk_core_get_boundaries(core, &min_rate, &max_rate);
clk_prepare_unlock();
seq_printf(s, "%lu\n", min_rate);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(clk_min_rate);
static int clk_max_rate_show(struct seq_file *s, void *data)
{
struct clk_core *core = s->private;
unsigned long min_rate, max_rate;
clk_prepare_lock();
clk_core_get_boundaries(core, &min_rate, &max_rate);
clk_prepare_unlock();
seq_printf(s, "%lu\n", max_rate);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
{
struct dentry *root;
@ -3075,6 +3099,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
core->dentry = root;
debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
debugfs_create_u32("clk_phase", 0444, root, &core->phase);
debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);

5
drivers/clk/davinci/pll.c
View File

@ -778,12 +778,15 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
int i;
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
if (!clk_data)
if (!clk_data) {
of_node_put(child);
return -ENOMEM;
}
clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
if (!clks) {
kfree(clk_data);
of_node_put(child);
return -ENOMEM;
}

1
drivers/clk/st/clk-flexgen.c
View File

@ -326,6 +326,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
return;
reg = of_iomap(pnode, 0);
of_node_put(pnode);
if (!reg)
return;

1
drivers/clk/st/clkgen-fsyn.c
View File

@ -67,7 +67,6 @@ struct clkgen_quadfs_data {
};
static const struct clk_ops st_quadfs_pll_c32_ops;
static const struct clk_ops st_quadfs_fs660c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
unsigned long output, struct stm_fs *fs);

13
drivers/clk/st/clkgen-pll.c
View File

@ -61,19 +61,6 @@ static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
/* 407 A0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
.pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
.ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
.idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
.num_odfs = 1,
.odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
.odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
.ops = &stm_pll3200c32_ops,
};
static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),

1
drivers/clk/ti/clk-814x.c
View File

@ -66,6 +66,7 @@ static int __init dm814x_adpll_early_init(void)
}
of_platform_populate(np, NULL, NULL, NULL);
of_node_put(np);
return 0;
}

1
drivers/clk/versatile/clk-versatile.c
View File

@ -70,6 +70,7 @@ static void __init cm_osc_setup(struct device_node *np,
return;
}
cm_base = of_iomap(parent, 0);
of_node_put(parent);
if (!cm_base) {
pr_err("could not remap core module base\n");
return;

17
include/linux/clk.h
View File

@ -239,7 +239,8 @@ static inline int clk_prepare(struct clk *clk)
return 0;
}
static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
static inline int __must_check
clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
{
might_sleep();
return 0;
@ -263,7 +264,8 @@ static inline void clk_unprepare(struct clk *clk)
{
might_sleep();
}
static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks)
static inline void clk_bulk_unprepare(int num_clks,
const struct clk_bulk_data *clks)
{
might_sleep();
}
@ -819,7 +821,8 @@ static inline int clk_enable(struct clk *clk)
return 0;
}
static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
static inline int __must_check clk_bulk_enable(int num_clks,
const struct clk_bulk_data *clks)
{
return 0;
}
@ -828,7 +831,7 @@ static inline void clk_disable(struct clk *clk) {}
static inline void clk_bulk_disable(int num_clks,
struct clk_bulk_data *clks) {}
const struct clk_bulk_data *clks) {}
static inline unsigned long clk_get_rate(struct clk *clk)
{
@ -917,8 +920,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
clk_unprepare(clk);
}
static inline int __must_check clk_bulk_prepare_enable(int num_clks,
struct clk_bulk_data *clks)
static inline int __must_check
clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks)
{
int ret;
@ -933,7 +936,7 @@ static inline int __must_check clk_bulk_prepare_enable(int num_clks,
}
static inline void clk_bulk_disable_unprepare(int num_clks,
struct clk_bulk_data *clks)
const struct clk_bulk_data *clks)
{
clk_bulk_disable(num_clks, clks);
clk_bulk_unprepare(num_clks, clks);