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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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pinctrl: lynxpoint: Add pin control data structures
In order to implement pin control for Intel Lynxpoint, we need data structures in which to store and pass along pin, community and SoC data information. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko
parent
54d371cf73
commit
cecddda7ca
@ -18,6 +18,128 @@
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "pinctrl-intel.h"
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#define COMMUNITY(p, n) \
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{ \
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.pin_base = (p), \
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.npins = (n), \
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}
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static const struct pinctrl_pin_desc lptlp_pins[] = {
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PINCTRL_PIN(0, "GP0_UART1_RXD"),
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PINCTRL_PIN(1, "GP1_UART1_TXD"),
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PINCTRL_PIN(2, "GP2_UART1_RTSB"),
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PINCTRL_PIN(3, "GP3_UART1_CTSB"),
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PINCTRL_PIN(4, "GP4_I2C0_SDA"),
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PINCTRL_PIN(5, "GP5_I2C0_SCL"),
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PINCTRL_PIN(6, "GP6_I2C1_SDA"),
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PINCTRL_PIN(7, "GP7_I2C1_SCL"),
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PINCTRL_PIN(8, "GP8"),
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PINCTRL_PIN(9, "GP9"),
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PINCTRL_PIN(10, "GP10"),
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PINCTRL_PIN(11, "GP11_SMBALERTB"),
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PINCTRL_PIN(12, "GP12_LANPHYPC"),
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PINCTRL_PIN(13, "GP13"),
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PINCTRL_PIN(14, "GP14"),
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PINCTRL_PIN(15, "GP15"),
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PINCTRL_PIN(16, "GP16_MGPIO9"),
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PINCTRL_PIN(17, "GP17_MGPIO10"),
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PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
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PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
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PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
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PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
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PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
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PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
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PINCTRL_PIN(24, "GP24_MGPIO0"),
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PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
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PINCTRL_PIN(26, "GP26_MGPIO5"),
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PINCTRL_PIN(27, "GP27_MGPIO6"),
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PINCTRL_PIN(28, "GP28_MGPIO7"),
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PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
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PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
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PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
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PINCTRL_PIN(32, "GP32_CLKRUNB"),
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PINCTRL_PIN(33, "GP33_DEVSLP0"),
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PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
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PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
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PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
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PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
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PINCTRL_PIN(38, "GP38_DEVSLP1"),
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PINCTRL_PIN(39, "GP39_DEVSLP2"),
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PINCTRL_PIN(40, "GP40_OC0B"),
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PINCTRL_PIN(41, "GP41_OC1B"),
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PINCTRL_PIN(42, "GP42_OC2B"),
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PINCTRL_PIN(43, "GP43_OC3B"),
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PINCTRL_PIN(44, "GP44"),
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PINCTRL_PIN(45, "GP45_TMS2"),
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PINCTRL_PIN(46, "GP46_TDO2"),
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PINCTRL_PIN(47, "GP47"),
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PINCTRL_PIN(48, "GP48"),
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PINCTRL_PIN(49, "GP49"),
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PINCTRL_PIN(50, "GP50"),
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PINCTRL_PIN(51, "GP51_GSXDOUT"),
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PINCTRL_PIN(52, "GP52_GSXSLOAD"),
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PINCTRL_PIN(53, "GP53_GSXDIN"),
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PINCTRL_PIN(54, "GP54_GSXSRESETB"),
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PINCTRL_PIN(55, "GP55_GSXCLK"),
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PINCTRL_PIN(56, "GP56"),
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PINCTRL_PIN(57, "GP57"),
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PINCTRL_PIN(58, "GP58"),
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PINCTRL_PIN(59, "GP59"),
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PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
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PINCTRL_PIN(61, "GP61_SUS_STATB"),
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PINCTRL_PIN(62, "GP62_SUSCLK"),
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PINCTRL_PIN(63, "GP63_SLP_S5B"),
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PINCTRL_PIN(64, "GP64_SDIO_CLK"),
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PINCTRL_PIN(65, "GP65_SDIO_CMD"),
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PINCTRL_PIN(66, "GP66_SDIO_D0"),
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PINCTRL_PIN(67, "GP67_SDIO_D1"),
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PINCTRL_PIN(68, "GP68_SDIO_D2"),
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PINCTRL_PIN(69, "GP69_SDIO_D3"),
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PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
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PINCTRL_PIN(71, "GP71_MPHYPC"),
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PINCTRL_PIN(72, "GP72_BATLOWB"),
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PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
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PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
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PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
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PINCTRL_PIN(76, "GP76_BMBUSYB"),
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PINCTRL_PIN(77, "GP77_PIRQAB"),
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PINCTRL_PIN(78, "GP78_PIRQBB"),
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PINCTRL_PIN(79, "GP79_PIRQCB"),
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PINCTRL_PIN(80, "GP80_PIRQDB"),
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PINCTRL_PIN(81, "GP81_SPKR"),
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PINCTRL_PIN(82, "GP82_RCINB"),
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PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
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PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
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PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
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PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
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PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
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PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
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PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
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PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
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PINCTRL_PIN(91, "GP91_UART0_RXD"),
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PINCTRL_PIN(92, "GP92_UART0_TXD"),
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PINCTRL_PIN(93, "GP93_UART0_RTSB"),
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PINCTRL_PIN(94, "GP94_UART0_CTSB"),
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};
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static const struct intel_community lptlp_communities[] = {
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COMMUNITY(0, 95),
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};
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static const struct intel_pinctrl_soc_data lptlp_soc_data = {
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.pins = lptlp_pins,
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.npins = ARRAY_SIZE(lptlp_pins),
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.communities = lptlp_communities,
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.ncommunities = ARRAY_SIZE(lptlp_communities),
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};
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/* LynxPoint chipset has support for 95 GPIO pins */
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#define LP_NUM_GPIO 95
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@ -477,8 +599,8 @@ static const struct dev_pm_ops lp_gpio_pm_ops = {
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};
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static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
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{ "INT33C7", 0 },
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{ "INT3437", 0 },
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{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
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{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
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