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drm/i915: Organize Fence registers for future enablement.

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Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's make
    this platforms subcases of Gen checks.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Rodrigo Vivi 2014-12-04 06:48:10 -08:00 committed by Daniel Vetter
parent e2c719b75c
commit ce38ab0593
2 changed files with 19 additions and 35 deletions
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17
drivers/gpu/drm/i915/i915_gem.c
View File

@ -3277,17 +3277,12 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
"bogus fence setup with stride: 0x%x, tiling mode: %i\n", "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
obj->stride, obj->tiling_mode); obj->stride, obj->tiling_mode);
switch (INTEL_INFO(dev)->gen) { if (IS_GEN2(dev))
case 9: i830_write_fence_reg(dev, reg, obj);
case 8: else if (IS_GEN3(dev))
case 7: i915_write_fence_reg(dev, reg, obj);
case 6: else if (INTEL_INFO(dev)->gen >= 4)
case 5: i965_write_fence_reg(dev, reg, obj);
case 4: i965_write_fence_reg(dev, reg, obj); break;
case 3: i915_write_fence_reg(dev, reg, obj); break;
case 2: i830_write_fence_reg(dev, reg, obj); break;
default: BUG();
}
/* And similarly be paranoid that no direct access to this region /* And similarly be paranoid that no direct access to this region
* is reordered to before the fence is installed. * is reordered to before the fence is installed.

37
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@ -764,32 +764,21 @@ static void i915_gem_record_fences(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int i; int i;
/* Fences */ if (IS_GEN3(dev) || IS_GEN2(dev)) {
switch (INTEL_INFO(dev)->gen) {
case 9:
case 8:
case 7:
case 6:
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
break;
case 5:
case 4:
for (i = 0; i < 16; i++)
error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
break;
case 3:
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
for (i = 0; i < 8; i++)
error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
case 2:
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
break; if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
for (i = 0; i < 8; i++)
default: error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
BUG(); (i * 4));
} } else if (IS_GEN5(dev) || IS_GEN4(dev))
for (i = 0; i < 16; i++)
error->fence[i] = I915_READ64(FENCE_REG_965_0 +
(i * 8));
else if (INTEL_INFO(dev)->gen >= 6)
for (i = 0; i < dev_priv->num_fence_regs; i++)
error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
(i * 8));
} }