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drm/amd/display: use vbios message to call smu for dpm level

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[Description]
use vbios message to call smu for dpm level
also only program dmdata in vsyncflip as HW requirement.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2019-09-17 20:28:40 -04:00 committed by Alex Deucher
parent 52883b36f7
commit ce10a0f39b
4 changed files with 28 additions and 2 deletions
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1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
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@ -50,4 +50,5 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr,
enum dc_clock_type clock_type, enum dc_clock_type clock_type,
struct dc_clock_config *clock_cfg); struct dc_clock_config *clock_cfg);
void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
#endif //__DCN20_CLK_MGR_H__ #endif //__DCN20_CLK_MGR_H__

8
drivers/gpu/drm/amd/display/dc/dc.h
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@ -245,6 +245,13 @@ enum wm_report_mode {
WM_REPORT_DEFAULT = 0, WM_REPORT_DEFAULT = 0,
WM_REPORT_OVERRIDE = 1, WM_REPORT_OVERRIDE = 1,
}; };
enum dtm_pstate{
dtm_level_p0 = 0,/*highest voltage*/
dtm_level_p1,
dtm_level_p2,
dtm_level_p3,
dtm_level_p4,/*when active_display_count = 0*/
};
enum dcn_pwr_state { enum dcn_pwr_state {
DCN_PWR_STATE_OPTIMIZED = 0, DCN_PWR_STATE_OPTIMIZED = 0,
@ -271,6 +278,7 @@ struct dc_clocks {
* optimization required * optimization required
*/ */
bool prev_p_state_change_support; bool prev_p_state_change_support;
enum dtm_pstate dtm_level;
int max_supported_dppclk_khz; int max_supported_dppclk_khz;
int max_supported_dispclk_khz; int max_supported_dispclk_khz;
int bw_dppclk_khz; /*a copy of dppclk_khz*/ int bw_dppclk_khz; /*a copy of dppclk_khz*/

6
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
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@ -2209,8 +2209,10 @@ static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
pipe_ctx->stream_res.stream_enc->id, true); pipe_ctx->stream_res.stream_enc->id, true);
if (link->dc->hwss.program_dmdata_engine) if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
link->dc->hwss.program_dmdata_engine(pipe_ctx); if (link->dc->hwss.program_dmdata_engine)
link->dc->hwss.program_dmdata_engine(pipe_ctx);
}
link->dc->hwss.update_info_frame(pipe_ctx); link->dc->hwss.update_info_frame(pipe_ctx);

15
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
View File

@ -184,6 +184,21 @@ struct clk_mgr_registers {
uint32_t MP1_SMN_C2PMSG_91; uint32_t MP1_SMN_C2PMSG_91;
}; };
enum clock_type {
clock_type_dispclk = 1,
clock_type_dcfclk,
clock_type_socclk,
clock_type_pixelclk,
clock_type_phyclk,
clock_type_dppclk,
clock_type_fclk,
clock_type_dcfdsclk,
clock_type_dscclk,
clock_type_uclk,
clock_type_dramclk,
};
struct state_dependent_clocks { struct state_dependent_clocks {
int display_clk_khz; int display_clk_khz;
int pixel_clk_khz; int pixel_clk_khz;