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dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and Tegra210 to make the names consistent. Keep the old name for now to keep device trees buildable until they have all been converted. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -337,7 +337,8 @@
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#define TEGRA124_CLK_CLK_OUT_3_MUX 308
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#define TEGRA124_CLK_CLK_OUT_3_MUX 308
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/* 309 */
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/* 309 */
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/* 310 */
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/* 310 */
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#define TEGRA124_CLK_SOR0_LVDS 311
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#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
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#define TEGRA124_CLK_SOR0_OUT 311
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#define TEGRA124_CLK_XUSB_SS_DIV2 312
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#define TEGRA124_CLK_XUSB_SS_DIV2 312
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#define TEGRA124_CLK_PLL_M_UD 313
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#define TEGRA124_CLK_PLL_M_UD 313
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@ -391,7 +391,8 @@
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#define TEGRA210_CLK_CLK_OUT_3_MUX 358
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#define TEGRA210_CLK_CLK_OUT_3_MUX 358
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#define TEGRA210_CLK_DSIA_MUX 359
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#define TEGRA210_CLK_DSIA_MUX 359
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#define TEGRA210_CLK_DSIB_MUX 360
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#define TEGRA210_CLK_DSIB_MUX 360
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#define TEGRA210_CLK_SOR0_LVDS 361
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#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */
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#define TEGRA210_CLK_SOR0_OUT 361
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#define TEGRA210_CLK_XUSB_SS_DIV2 362
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#define TEGRA210_CLK_XUSB_SS_DIV2 362
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#define TEGRA210_CLK_PLL_M_UD 363
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#define TEGRA210_CLK_PLL_M_UD 363
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