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dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Convert USB DWC3 bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Felipe Balbi <balbi@kernel.org>
This commit is contained in:
Sandeep Maheswaram
Felipe Balbi
parent
fcd2def663
commit
cd4b54e2ae
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Qualcomm SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: Compatible list, contains
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"qcom,dwc3"
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"qcom,msm8996-dwc3" for msm8996 SOC.
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"qcom,msm8998-dwc3" for msm8998 SOC.
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"qcom,sdm845-dwc3" for sdm845 SOC.
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- reg: Offset and length of register set for QSCRATCH wrapper
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- power-domains: specifies a phandle to PM domain provider node
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"core" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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"mock_utmi" Mock utmi clock needed for ITP/SOF generation in
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host mode. Its frequency should be 19.2MHz.
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"sleep" Sleep clock, used for wakeup when USB3 core goes
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into low power mode (U3).
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Optional clocks:
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"iface" System bus AXI clock.
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Not present on "qcom,msm8996-dwc3" compatible.
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"cfg_noc" System Config NOC clock.
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Not present on "qcom,msm8996-dwc3" compatible.
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- assigned-clocks: Should be:
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MOCK_UTMI_CLK
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MASTER_CLK
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- assigned-clock-rates: Should be:
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19.2Mhz (192000000) for MOCK_UTMI_CLK
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>=125Mhz (125000000) for MASTER_CLK in SS mode
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>=60Mhz (60000000) for MASTER_CLK in HS mode
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Optional properties:
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- resets: Phandle to reset control that resets core and wrapper.
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- interrupts: specifies interrupts from controller wrapper used
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to wakeup from low power/susepnd state. Must contain
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one or more entry for interrupt-names property
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- interrupt-names: Must include the following entries:
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- "hs_phy_irq": The interrupt that is asserted when a
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wakeup event is received on USB2 bus
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- "ss_phy_irq": The interrupt that is asserted when a
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wakeup event is received on USB3 bus
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- "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
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interrupts for any wakeup event on DM and DP lines
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- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
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Used when dwc3 operates without SSPHY and only
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HS/FS/LS modes are supported.
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Phy documentation is provided in the following places:
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Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
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Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml - USB2 QUSB2 PHY
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Example device nodes:
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hs_phy: phy@100f8800 {
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compatible = "qcom,qusb2-v2-phy";
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...
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};
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ss_phy: phy@100f8830 {
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compatible = "qcom,qmp-v3-usb3-phy";
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...
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};
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usb3_0: usb30@a6f8800 {
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compatible = "qcom,dwc3";
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reg = <0xa6f8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core", "mock_utmi", "sleep";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <133000000>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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qcom,select-utmi-as-pipe-clk;
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dwc3@10000000 {
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compatible = "snps,dwc3";
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reg = <0x10000000 0xcd00>;
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interrupts = <0 205 0x4>;
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phys = <&hs_phy>, <&ss_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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dr_mode = "host";
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};
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};
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158
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Normal file
158
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Normal file
@ -0,0 +1,158 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Manu Gautam <mgautam@codeaurora.org>
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8996-dwc3
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- qcom,msm8998-dwc3
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- qcom,sdm845-dwc3
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- const: qcom,dwc3
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reg:
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description: Offset and length of register set for QSCRATCH wrapper
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maxItems: 1
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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power-domains:
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description: specifies a phandle to PM domain provider node
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maxItems: 1
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clocks:
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description:
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A list of phandle and clock-specifier pairs for the clocks
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listed in clock-names.
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items:
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- description: System Config NOC clock.
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- description: Master/Core clock, has to be >= 125 MHz
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for SS operation and >= 60MHz for HS operation.
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- description: System bus AXI clock.
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- description: Mock utmi clock needed for ITP/SOF generation
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in host mode. Its frequency should be 19.2MHz.
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- description: Sleep clock, used for wakeup when
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USB3 core goes into low power mode (U3).
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clock-names:
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items:
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- const: cfg_noc
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- const: core
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- const: iface
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- const: mock_utmi
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- const: sleep
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assigned-clocks:
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items:
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- description: Phandle and clock specifier of MOCK_UTMI_CLK.
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- description: Phandle and clock specifoer of MASTER_CLK.
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assigned-clock-rates:
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maxItems: 2
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items:
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- description: Must be 19.2MHz (19200000).
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- description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
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resets:
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maxItems: 1
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interrupts:
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items:
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- description: The interrupt that is asserted
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when a wakeup event is received on USB2 bus.
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- description: The interrupt that is asserted
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when a wakeup event is received on USB3 bus.
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- description: Wakeup event on DM line.
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- description: Wakeup event on DP line.
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interrupt-names:
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items:
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- const: hs_phy_irq
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- const: ss_phy_irq
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- const: dm_hs_phy_irq
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- const: dp_hs_phy_irq
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qcom,select-utmi-as-pipe-clk:
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description:
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If present, disable USB3 pipe_clk requirement.
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Used when dwc3 operates without SSPHY and only
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HS/FS/LS modes are supported.
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type: boolean
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# Required child node:
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patternProperties:
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"^dwc3@[0-9a-f]+$":
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type: object
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description:
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A child node must exist to represent the core DWC3 IP block
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The content of the node is defined in dwc3.txt.
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- power-domains
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- clocks
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- clock-names
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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usb@a6f8800 {
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compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <150000000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x740 0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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