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ARM: dts: sun7i: Add A20 SRAM and SRAM controller

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The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[hdegoede@redhat.com: Do not change soc node name, change compatible to
 sun4i-a10-sram-controller to match the driver change]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard 2015-03-26 15:53:44 +01:00
parent e6f51e4bd2
commit ccb4ada2f1
1 changed files with 34 additions and 0 deletions
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34
arch/arm/boot/dts/sun7i-a20.dtsi
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@ -521,12 +521,46 @@ clk_out_b: clk@01c201f4 {
};
};
/*
* Note we use the address where the mmio registers start, not where
* the SRAM blocks start, this cannot be changed because that would be
* a devicetree ABI change.
*/
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram@00000000 {
compatible = "allwinner,sun4i-a10-sram";
reg = <0x00000000 0x4000>;
allwinner,sram-name = "A1";
};
sram@00004000 {
compatible = "allwinner,sun4i-a10-sram";
reg = <0x00004000 0x4000>;
allwinner,sram-name = "A2";
};
sram@00008000 {
compatible = "allwinner,sun4i-a10-sram";
reg = <0x00008000 0x4000>;
allwinner,sram-name = "A3-A4";
};
sram@00010000 {
compatible = "allwinner,sun4i-a10-sram";
reg = <0x00010000 0x1000>;
allwinner,sram-name = "D";
};
sram-controller@01c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
};
nmi_intc: interrupt-controller@01c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;