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arm64: dts: rockchip: Add missing cooling device properties for CPUs

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The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Viresh Kumar 2018-05-25 11:10:05 +05:30 committed by Heiko Stuebner
parent ea41d63b54
commit cc9b091803
3 changed files with 15 additions and 4 deletions
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3
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -52,6 +52,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@ -63,6 +64,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@ -74,6 +76,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;

8
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -76,7 +76,6 @@ cpu_l0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
@ -85,6 +84,7 @@ cpu_l1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_l2: cpu@2 {
@ -92,6 +92,7 @@ cpu_l2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_l3: cpu@3 {
@ -99,6 +100,7 @@ cpu_l3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_b0: cpu@100 {
@ -106,7 +108,6 @@ cpu_b0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
@ -115,6 +116,7 @@ cpu_b1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_b2: cpu@102 {
@ -122,6 +124,7 @@ cpu_b2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_b3: cpu@103 {
@ -129,6 +132,7 @@ cpu_b3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
};

8
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -71,8 +71,8 @@ cpu_l0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@ -82,6 +82,7 @@ cpu_l1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@ -91,6 +92,7 @@ cpu_l2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@ -100,6 +102,7 @@ cpu_l3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@ -108,8 +111,8 @@ cpu_b0: cpu@100 {
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
};
@ -119,6 +122,7 @@ cpu_b1: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
};
};