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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 14:00:54 +07:00
Merge master.kernel.org:/home/rmk/linux-2.6-serial
This commit is contained in:
commit
cc918c7ab7
@ -296,7 +296,7 @@ static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
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#endif
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static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
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static unsigned int serial_in(struct uart_8250_port *up, int offset)
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{
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offset = map_8250_in_reg(up, offset) << up->port.regshift;
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@ -321,7 +321,7 @@ static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
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}
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}
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static _INLINE_ void
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static void
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serial_out(struct uart_8250_port *up, int offset, int value)
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{
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offset = map_8250_out_reg(up, offset) << up->port.regshift;
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@ -1131,7 +1131,7 @@ static void serial8250_enable_ms(struct uart_port *port)
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serial_out(up, UART_IER, up->ier);
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}
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static _INLINE_ void
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static void
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receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
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{
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struct tty_struct *tty = up->port.info->tty;
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@ -1217,7 +1217,7 @@ receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
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*status = lsr;
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}
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static _INLINE_ void transmit_chars(struct uart_8250_port *up)
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static void transmit_chars(struct uart_8250_port *up)
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{
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struct circ_buf *xmit = &up->port.info->xmit;
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int count;
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@ -1255,25 +1255,24 @@ static _INLINE_ void transmit_chars(struct uart_8250_port *up)
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__stop_tx(up);
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}
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static _INLINE_ void check_modem_status(struct uart_8250_port *up)
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static unsigned int check_modem_status(struct uart_8250_port *up)
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{
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int status;
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unsigned int status = serial_in(up, UART_MSR);
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status = serial_in(up, UART_MSR);
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if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
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if (status & UART_MSR_TERI)
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up->port.icount.rng++;
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if (status & UART_MSR_DDSR)
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up->port.icount.dsr++;
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if (status & UART_MSR_DDCD)
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uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
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if (status & UART_MSR_DCTS)
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uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
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if ((status & UART_MSR_ANY_DELTA) == 0)
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return;
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wake_up_interruptible(&up->port.info->delta_msr_wait);
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}
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if (status & UART_MSR_TERI)
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up->port.icount.rng++;
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if (status & UART_MSR_DDSR)
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up->port.icount.dsr++;
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if (status & UART_MSR_DDCD)
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uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
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if (status & UART_MSR_DCTS)
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uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
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wake_up_interruptible(&up->port.info->delta_msr_wait);
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return status;
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}
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/*
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@ -1282,7 +1281,11 @@ static _INLINE_ void check_modem_status(struct uart_8250_port *up)
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static inline void
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serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
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{
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unsigned int status = serial_inp(up, UART_LSR);
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unsigned int status;
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spin_lock(&up->port.lock);
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status = serial_inp(up, UART_LSR);
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DEBUG_INTR("status = %x...", status);
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@ -1291,6 +1294,8 @@ serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
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check_modem_status(up);
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if (status & UART_LSR_THRE)
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transmit_chars(up);
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spin_unlock(&up->port.lock);
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}
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/*
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@ -1326,9 +1331,7 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *r
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iir = serial_in(up, UART_IIR);
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if (!(iir & UART_IIR_NO_INT)) {
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spin_lock(&up->port.lock);
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serial8250_handle_port(up, regs);
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spin_unlock(&up->port.lock);
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handled = 1;
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@ -1427,11 +1430,8 @@ static void serial8250_timeout(unsigned long data)
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unsigned int iir;
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iir = serial_in(up, UART_IIR);
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if (!(iir & UART_IIR_NO_INT)) {
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spin_lock(&up->port.lock);
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if (!(iir & UART_IIR_NO_INT))
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serial8250_handle_port(up, NULL);
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spin_unlock(&up->port.lock);
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}
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timeout = up->port.timeout;
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timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
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@ -1454,10 +1454,10 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
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static unsigned int serial8250_get_mctrl(struct uart_port *port)
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{
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struct uart_8250_port *up = (struct uart_8250_port *)port;
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unsigned char status;
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unsigned int status;
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unsigned int ret;
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status = serial_in(up, UART_MSR);
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status = check_modem_status(up);
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ret = 0;
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if (status & UART_MSR_DCD)
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@ -2300,9 +2300,7 @@ static int __init find_port(struct uart_port *p)
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for (line = 0; line < UART_NR; line++) {
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port = &serial8250_ports[line].port;
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if (p->iotype == port->iotype &&
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p->iobase == port->iobase &&
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p->membase == port->membase)
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if (uart_match_port(p, port))
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return line;
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}
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return -ENODEV;
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@ -51,12 +51,6 @@ struct serial8250_config {
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#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
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#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
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#if defined(__i386__) && (defined(CONFIG_M386) || defined(CONFIG_M486))
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#define _INLINE_ inline
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#else
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#define _INLINE_
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#endif
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#define PROBE_RSA (1 << 0)
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#define PROBE_ANY (~0)
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@ -837,8 +837,8 @@ static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
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return quirk;
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}
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static _INLINE_ int
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get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
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static inline int get_pci_irq(struct pci_dev *dev,
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struct pciserial_board *board)
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{
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if (board->flags & FL_NOIRQ)
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return 0;
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@ -853,14 +853,15 @@ get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
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* driver_data member.
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*
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* The makeup of these names are:
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* pbn_bn{_bt}_n_baud
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* pbn_bn{_bt}_n_baud{_offsetinhex}
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*
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* bn = PCI BAR number
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* bt = Index using PCI BARs
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* n = number of serial ports
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* baud = baud rate
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* bn = PCI BAR number
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* bt = Index using PCI BARs
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* n = number of serial ports
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* baud = baud rate
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* offsetinhex = offset for each sequential port (in hex)
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*
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* This table is sorted by (in order): baud, bt, bn, n.
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* This table is sorted by (in order): bn, bt, baud, offsetindex, n.
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*
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* Please note: in theory if n = 1, _bt infix should make no difference.
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* ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
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@ -881,6 +882,13 @@ enum pci_board_num_t {
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pbn_b0_4_1152000,
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pbn_b0_2_1843200,
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pbn_b0_4_1843200,
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pbn_b0_2_1843200_200,
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pbn_b0_4_1843200_200,
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pbn_b0_8_1843200_200,
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pbn_b0_bt_1_115200,
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pbn_b0_bt_2_115200,
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pbn_b0_bt_8_115200,
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@ -904,6 +912,8 @@ enum pci_board_num_t {
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pbn_b1_4_921600,
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pbn_b1_8_921600,
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pbn_b1_2_1250000,
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pbn_b1_bt_2_921600,
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pbn_b1_1_1382400,
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@ -1029,6 +1039,38 @@ static struct pciserial_board pci_boards[] __devinitdata = {
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.uart_offset = 8,
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},
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[pbn_b0_2_1843200] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 1843200,
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.uart_offset = 8,
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},
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[pbn_b0_4_1843200] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 1843200,
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.uart_offset = 8,
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},
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[pbn_b0_2_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_4_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_8_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_bt_1_115200] = {
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.flags = FL_BASE0|FL_BASE_BARS,
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.num_ports = 1,
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@ -1141,6 +1183,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
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.base_baud = 921600,
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.uart_offset = 8,
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},
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[pbn_b1_2_1250000] = {
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.flags = FL_BASE1,
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.num_ports = 2,
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.base_baud = 1250000,
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.uart_offset = 8,
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},
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[pbn_b1_bt_2_921600] = {
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.flags = FL_BASE1|FL_BASE_BARS,
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@ -1801,6 +1849,66 @@ static struct pci_device_id serial_pci_tbl[] = {
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
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pbn_b1_4_921600 },
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{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
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pbn_b1_2_1250000 },
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{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
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pbn_b0_2_1843200 },
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{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
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pbn_b0_4_1843200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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@ -2307,7 +2307,7 @@ int uart_match_port(struct uart_port *port1, struct uart_port *port2)
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return (port1->iobase == port2->iobase) &&
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(port1->hub6 == port2->hub6);
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case UPIO_MEM:
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return (port1->membase == port2->membase);
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return (port1->mapbase == port2->mapbase);
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}
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return 0;
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}
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@ -1583,6 +1583,23 @@
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332
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#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
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