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clk: qoriq: add more PLL divider clocks support
More PLL divider clocks are needed by clock consumer IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -34,6 +34,7 @@
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#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
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#define CGB_PLL1 4
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#define CGB_PLL2 5
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#define MAX_PLL_DIV 16
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struct clockgen_pll_div {
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struct clk *clk;
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@ -41,7 +42,7 @@ struct clockgen_pll_div {
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};
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struct clockgen_pll {
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struct clockgen_pll_div div[8];
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struct clockgen_pll_div div[MAX_PLL_DIV];
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};
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#define CLKSEL_VALID 1
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@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
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int ret;
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/*
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* For platform PLL, there are 8 divider clocks.
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* For platform PLL, there are MAX_PLL_DIV divider clocks.
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* For core PLL, there are 4 divider clocks at most.
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*/
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if (idx != PLATFORM_PLL && i >= 4)
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