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drm/i915: Use masked write for Context Status Buffer Pointer

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This register needs to be updated with masked writes.

This was found by code inspection and comparison with Bspec and
doesn't seem to fix any known issue.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
[danvet: Add note about impact.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Mika Kuoppala 2015-08-06 17:00:59 +03:00 committed by Daniel Vetter
parent 9bd9dfb4f9
commit cc53699b25
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_lrc.c
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@ -521,7 +521,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
ring->next_context_status_buffer = write_pointer % 6;
I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
((u32)ring->next_context_status_buffer & 0x07) << 8);
_MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
}
static int execlists_context_queue(struct drm_i915_gem_request *request)