mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 22:41:11 +07:00
drm/amdgpu: add VCN2.5 VCPU start and stop
HW engine initialization and suspend sequences. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Liu
Alex Deucher
parent
28c17d7207
commit
cbead2bdfc
@ -307,6 +307,446 @@ static int vcn_v2_5_resume(void *handle)
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return r;
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}
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/**
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* vcn_v2_5_mc_resume - memory controller programming
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*
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* @adev: amdgpu_device pointer
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*
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* Let the VCN memory controller know it's offsets
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*/
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static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
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{
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uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
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uint32_t offset;
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/* cache window 0: fw */
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
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offset = 0;
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} else {
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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lower_32_bits(adev->vcn.gpu_addr));
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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upper_32_bits(adev->vcn.gpu_addr));
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offset = size;
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/* No signed header for now from firmware
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
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*/
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
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}
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
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/* cache window 1: stack */
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
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lower_32_bits(adev->vcn.gpu_addr + offset));
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
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upper_32_bits(adev->vcn.gpu_addr + offset));
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
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/* cache window 2: context */
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
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lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
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upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
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}
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/**
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* vcn_v2_5_disable_clock_gating - disable VCN clock gating
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*
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* @adev: amdgpu_device pointer
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* @sw: enable SW clock gating
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*
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* Disable clock gating for VCN block
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*/
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static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
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{
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uint32_t data;
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int ret = 0;
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/* UVD disable CGC */
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data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
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data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
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data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
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data &= ~(UVD_CGC_GATE__SYS_MASK
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| UVD_CGC_GATE__UDEC_MASK
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| UVD_CGC_GATE__MPEG2_MASK
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| UVD_CGC_GATE__REGS_MASK
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| UVD_CGC_GATE__RBC_MASK
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| UVD_CGC_GATE__LMI_MC_MASK
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| UVD_CGC_GATE__LMI_UMC_MASK
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| UVD_CGC_GATE__IDCT_MASK
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| UVD_CGC_GATE__MPRD_MASK
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| UVD_CGC_GATE__MPC_MASK
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| UVD_CGC_GATE__LBSI_MASK
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| UVD_CGC_GATE__LRBBM_MASK
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| UVD_CGC_GATE__UDEC_RE_MASK
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| UVD_CGC_GATE__UDEC_CM_MASK
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| UVD_CGC_GATE__UDEC_IT_MASK
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| UVD_CGC_GATE__UDEC_DB_MASK
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| UVD_CGC_GATE__UDEC_MP_MASK
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| UVD_CGC_GATE__WCB_MASK
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| UVD_CGC_GATE__VCPU_MASK
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| UVD_CGC_GATE__MMSCH_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
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SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
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data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
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data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
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| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
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| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
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| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
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| UVD_CGC_CTRL__SYS_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MODE_MASK
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| UVD_CGC_CTRL__MPEG2_MODE_MASK
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| UVD_CGC_CTRL__REGS_MODE_MASK
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| UVD_CGC_CTRL__RBC_MODE_MASK
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| UVD_CGC_CTRL__LMI_MC_MODE_MASK
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| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
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| UVD_CGC_CTRL__IDCT_MODE_MASK
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| UVD_CGC_CTRL__MPRD_MODE_MASK
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| UVD_CGC_CTRL__MPC_MODE_MASK
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| UVD_CGC_CTRL__LBSI_MODE_MASK
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| UVD_CGC_CTRL__LRBBM_MODE_MASK
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| UVD_CGC_CTRL__WCB_MODE_MASK
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| UVD_CGC_CTRL__VCPU_MODE_MASK
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| UVD_CGC_CTRL__MMSCH_MODE_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
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/* turn on */
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data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
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data |= (UVD_SUVD_CGC_GATE__SRE_MASK
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| UVD_SUVD_CGC_GATE__SIT_MASK
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| UVD_SUVD_CGC_GATE__SMP_MASK
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| UVD_SUVD_CGC_GATE__SCM_MASK
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| UVD_SUVD_CGC_GATE__SDB_MASK
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| UVD_SUVD_CGC_GATE__SRE_H264_MASK
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| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SIT_H264_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SCM_H264_MASK
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| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SDB_H264_MASK
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| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SCLR_MASK
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| UVD_SUVD_CGC_GATE__UVD_SC_MASK
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| UVD_SUVD_CGC_GATE__ENT_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
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| UVD_SUVD_CGC_GATE__SITE_MASK
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| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
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| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
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| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
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| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
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| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
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data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
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data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
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| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
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| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
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}
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/**
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* vcn_v2_5_enable_clock_gating - enable VCN clock gating
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*
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* @adev: amdgpu_device pointer
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* @sw: enable SW clock gating
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*
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* Enable clock gating for VCN block
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*/
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static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
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{
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uint32_t data = 0;
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/* enable UVD CGC */
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data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
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data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
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data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
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| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
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| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
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| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
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| UVD_CGC_CTRL__SYS_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MODE_MASK
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| UVD_CGC_CTRL__MPEG2_MODE_MASK
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| UVD_CGC_CTRL__REGS_MODE_MASK
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| UVD_CGC_CTRL__RBC_MODE_MASK
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| UVD_CGC_CTRL__LMI_MC_MODE_MASK
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| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
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| UVD_CGC_CTRL__IDCT_MODE_MASK
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| UVD_CGC_CTRL__MPRD_MODE_MASK
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| UVD_CGC_CTRL__MPC_MODE_MASK
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| UVD_CGC_CTRL__LBSI_MODE_MASK
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| UVD_CGC_CTRL__LRBBM_MODE_MASK
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| UVD_CGC_CTRL__WCB_MODE_MASK
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| UVD_CGC_CTRL__VCPU_MODE_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
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data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
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| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
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| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
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WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
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}
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static int vcn_v2_5_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->vcn.ring_dec;
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uint32_t rb_bufsz, tmp;
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int i, j, r;
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/* disable register anti-hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
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~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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/* set uvd status busy */
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tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
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WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
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/*SW clock gating */
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vcn_v2_5_disable_clock_gating(adev);
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/* enable VCPU clock */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
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/* disable master interrupt */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
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~UVD_MASTINT_EN__VCPU_EN_MASK);
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/* setup mmUVD_LMI_CTRL */
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tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
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tmp &= ~0xff;
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WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 0x8|
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UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
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/* setup mmUVD_MPC_CNTL */
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tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
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tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
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tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
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WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
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/* setup UVD_MPC_SET_MUXA0 */
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
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((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
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/* setup UVD_MPC_SET_MUXB0 */
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
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((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
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(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
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(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
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/* setup mmUVD_MPC_SET_MUX */
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
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((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
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(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
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(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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vcn_v2_5_mc_resume(adev);
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/* VCN global tiling registers */
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WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* enable LMI MC and UMC channels */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* unblock VCPU register access */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL), 0,
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~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
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if (status & 2)
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break;
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if (amdgpu_emu_mode == 1)
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msleep(500);
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else
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mdelay(10);
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}
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r = 0;
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if (status & 2)
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break;
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DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__BLK_RST_MASK,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
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~UVD_VCPU_CNTL__BLK_RST_MASK);
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mdelay(10);
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r = -1;
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}
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if (r) {
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DRM_ERROR("VCN decode not responding, giving up!!!\n");
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return r;
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}
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/* enable master interrupt */
|
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
|
||||
UVD_MASTINT_EN__VCPU_EN_MASK,
|
||||
~UVD_MASTINT_EN__VCPU_EN_MASK);
|
||||
|
||||
/* clear the busy bit of VCN_STATUS */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
|
||||
~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
|
||||
|
||||
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
|
||||
|
||||
/* force RBC into idle state */
|
||||
rb_bufsz = order_base_2(ring->ring_size);
|
||||
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
|
||||
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
|
||||
|
||||
/* programm the RB_BASE for ring buffer */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
|
||||
lower_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
|
||||
upper_32_bits(ring->gpu_addr));
|
||||
|
||||
/* Initialize the ring buffer's read and write pointers */
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
|
||||
|
||||
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
|
||||
lower_32_bits(ring->wptr));
|
||||
ring = &adev->vcn.ring_enc[0];
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
|
||||
|
||||
ring = &adev->vcn.ring_enc[1];
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int vcn_v2_5_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t tmp;
|
||||
int r;
|
||||
|
||||
/* wait for vcn idle */
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__READ_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_MASK |
|
||||
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* block LMI UMC channel */
|
||||
tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
|
||||
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
|
||||
WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
|
||||
|
||||
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
|
||||
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
|
||||
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* block VCPU register access */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL),
|
||||
UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
|
||||
~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
|
||||
|
||||
/* reset VCPU */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
|
||||
UVD_VCPU_CNTL__BLK_RST_MASK,
|
||||
~UVD_VCPU_CNTL__BLK_RST_MASK);
|
||||
|
||||
/* disable VCPU clock */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
|
||||
~(UVD_VCPU_CNTL__CLK_EN_MASK));
|
||||
|
||||
/* clear status */
|
||||
WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
|
||||
|
||||
vcn_v2_5_enable_clock_gating(adev);
|
||||
|
||||
/* enable register anti-hang mechanism */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
|
||||
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
|
||||
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool vcn_v2_5_is_idle(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
@ -328,13 +768,38 @@ static int vcn_v2_5_wait_for_idle(void *handle)
|
||||
static int vcn_v2_5_set_clockgating_state(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
||||
|
||||
if (enable) {
|
||||
if (vcn_v2_5_is_idle(handle))
|
||||
return -EBUSY;
|
||||
vcn_v2_5_enable_clock_gating(adev);
|
||||
} else {
|
||||
vcn_v2_5_disable_clock_gating(adev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vcn_v2_5_set_powergating_state(void *handle,
|
||||
enum amd_powergating_state state)
|
||||
{
|
||||
return 0;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
int ret;
|
||||
|
||||
if(state == adev->vcn.cur_state)
|
||||
return 0;
|
||||
|
||||
if (state == AMD_PG_STATE_GATE)
|
||||
ret = vcn_v2_5_stop(adev);
|
||||
else
|
||||
ret = vcn_v2_5_start(adev);
|
||||
|
||||
if(!ret)
|
||||
adev->vcn.cur_state = state;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user