AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-01-18 10:56:12 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/amd/display: use different sr latencies for dpm0 dcn bw calc

Browse Source 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2017-06-20 17:24:23 -04:00 committed by Alex Deucher
parent 92af86fa7c
commit cb26f8925c
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View File

@ -906,6 +906,16 @@ bool dcn_validate_bandwidth(
scaler_settings_calculation(v);
mode_support_and_system_configuration(v);
if (v->voltage_level == 0) {
struct core_dc *dc_core = DC_TO_CORE(&dc->public);
v->sr_enter_plus_exit_time = 9.466f;
v->sr_exit_time = 7.849f;
dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
mode_support_and_system_configuration(v);
}
if (v->voltage_level != 5) {
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
@ -1013,6 +1023,14 @@ bool dcn_validate_bandwidth(
&dc->dml, context, pool);
}
if (v->voltage_level == 0) {
struct core_dc *dc_core = DC_TO_CORE(&dc->public);
dc_core->dml.soc.sr_enter_plus_exit_time_us =
dc_core->dcn_soc.sr_enter_plus_exit_time;
dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time;
}
kernel_fpu_end();
return v->voltage_level != 5;
}