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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[PATCH] synclink_gt: add bisync and monosync modes
Add bisync and monosync serial protocol support to the synclink_gt driver. Signed-off-by: Paul Fulghum <paulkf@microgate.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Paul Fulghum
Linus Torvalds
parent
3c1fcfe229
commit
cb10dc9ac7
@ -461,7 +461,7 @@ static int adapter_test(struct slgt_info *info);
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static void reset_adapter(struct slgt_info *info);
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static void reset_port(struct slgt_info *info);
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static void async_mode(struct slgt_info *info);
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static void hdlc_mode(struct slgt_info *info);
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static void sync_mode(struct slgt_info *info);
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static void rx_stop(struct slgt_info *info);
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static void rx_start(struct slgt_info *info);
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@ -881,7 +881,9 @@ static int write(struct tty_struct *tty,
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if (!count)
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goto cleanup;
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if (info->params.mode == MGSL_MODE_RAW) {
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if (info->params.mode == MGSL_MODE_RAW ||
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info->params.mode == MGSL_MODE_MONOSYNC ||
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info->params.mode == MGSL_MODE_BISYNC) {
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unsigned int bufs_needed = (count/DMABUFSIZE);
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unsigned int bufs_free = free_tbuf_count(info);
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if (count % DMABUFSIZE)
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@ -1897,6 +1899,8 @@ static void bh_handler(void* context)
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while(rx_get_frame(info));
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break;
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case MGSL_MODE_RAW:
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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while(rx_get_buf(info));
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break;
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}
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@ -2362,10 +2366,9 @@ static void program_hw(struct slgt_info *info)
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rx_stop(info);
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tx_stop(info);
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if (info->params.mode == MGSL_MODE_HDLC ||
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info->params.mode == MGSL_MODE_RAW ||
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if (info->params.mode != MGSL_MODE_ASYNC ||
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info->netcount)
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hdlc_mode(info);
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sync_mode(info);
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else
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async_mode(info);
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@ -2564,6 +2567,10 @@ static int rx_enable(struct slgt_info *info, int enable)
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if (enable) {
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if (!info->rx_enabled)
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rx_start(info);
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else if (enable == 2) {
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/* force hunt mode (write 1 to RCR[3]) */
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wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
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}
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} else {
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if (info->rx_enabled)
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rx_stop(info);
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@ -3748,7 +3755,7 @@ static void tx_start(struct slgt_info *info)
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{
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if (!info->tx_enabled) {
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wr_reg16(info, TCR,
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(unsigned short)(rd_reg16(info, TCR) | BIT1));
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(unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
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info->tx_enabled = TRUE;
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}
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@ -3775,13 +3782,18 @@ static void tx_start(struct slgt_info *info)
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tdma_reset(info);
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/* set 1st descriptor address */
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wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
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if (info->params.mode == MGSL_MODE_RAW)
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switch(info->params.mode) {
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case MGSL_MODE_RAW:
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
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else
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break;
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default:
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wr_reg32(info, TDCSR, BIT0); /* DMA enable */
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}
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}
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if (info->params.mode != MGSL_MODE_RAW) {
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if (info->params.mode == MGSL_MODE_HDLC) {
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info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
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add_timer(&info->tx_timer);
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}
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@ -3814,7 +3826,6 @@ static void tx_stop(struct slgt_info *info)
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/* reset and disable transmitter */
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val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
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wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
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wr_reg16(info, TCR, val); /* clear reset */
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slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
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@ -3982,7 +3993,7 @@ static void async_mode(struct slgt_info *info)
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enable_loopback(info);
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}
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static void hdlc_mode(struct slgt_info *info)
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static void sync_mode(struct slgt_info *info)
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{
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unsigned short val;
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@ -3992,7 +4003,7 @@ static void hdlc_mode(struct slgt_info *info)
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/* TCR (tx control)
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*
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* 15..13 mode, 000=HDLC 001=raw sync
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* 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
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* 12..10 encoding
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* 09 CRC enable
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* 08 CRC32
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@ -4006,8 +4017,11 @@ static void hdlc_mode(struct slgt_info *info)
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*/
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val = 0;
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if (info->params.mode == MGSL_MODE_RAW)
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val |= BIT13;
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switch(info->params.mode) {
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case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
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case MGSL_MODE_BISYNC: val |= BIT15; break;
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case MGSL_MODE_RAW: val |= BIT13; break;
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}
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if (info->if_mode & MGSL_INTERFACE_RTS_EN)
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val |= BIT7;
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@ -4058,7 +4072,7 @@ static void hdlc_mode(struct slgt_info *info)
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/* RCR (rx control)
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*
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* 15..13 mode, 000=HDLC 001=raw sync
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* 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
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* 12..10 encoding
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* 09 CRC enable
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* 08 CRC32
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@ -4069,8 +4083,11 @@ static void hdlc_mode(struct slgt_info *info)
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*/
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val = 0;
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if (info->params.mode == MGSL_MODE_RAW)
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val |= BIT13;
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switch(info->params.mode) {
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case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
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case MGSL_MODE_BISYNC: val |= BIT15; break;
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case MGSL_MODE_RAW: val |= BIT13; break;
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}
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switch(info->params.encoding)
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{
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@ -4309,10 +4326,15 @@ static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last
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while(!done) {
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/* reset current buffer for reuse */
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info->rbufs[i].status = 0;
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if (info->params.mode == MGSL_MODE_RAW)
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switch(info->params.mode) {
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case MGSL_MODE_RAW:
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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set_desc_count(info->rbufs[i], info->raw_rx_size);
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else
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break;
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default:
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set_desc_count(info->rbufs[i], DMABUFSIZE);
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}
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if (i == last)
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done = 1;
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@ -4477,13 +4499,24 @@ static int rx_get_frame(struct slgt_info *info)
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static int rx_get_buf(struct slgt_info *info)
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{
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unsigned int i = info->rbuf_current;
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unsigned int count;
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if (!desc_complete(info->rbufs[i]))
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return 0;
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DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
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DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
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ldisc_receive_buf(info->tty, info->rbufs[i].buf,
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info->flag_buf, desc_count(info->rbufs[i]));
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count = desc_count(info->rbufs[i]);
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switch(info->params.mode) {
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case MGSL_MODE_MONOSYNC:
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case MGSL_MODE_BISYNC:
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/* ignore residue in byte synchronous modes */
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if (desc_residue(info->rbufs[i]))
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count--;
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break;
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}
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DBGDATA(info, info->rbufs[i].buf, count, "rx");
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DBGINFO(("rx_get_buf size=%d\n", count));
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if (count)
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ldisc_receive_buf(info->tty, info->rbufs[i].buf,
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info->flag_buf, count);
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free_rbufs(info, i, i);
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return 1;
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}
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@ -4549,8 +4582,13 @@ static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
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size -= count;
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buf += count;
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if (!size && info->params.mode != MGSL_MODE_RAW)
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set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
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/*
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* set EOF bit for last buffer of HDLC frame or
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* for every buffer in raw mode
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*/
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if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
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info->params.mode == MGSL_MODE_RAW)
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set_desc_eof(*d, 1);
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else
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set_desc_eof(*d, 0);
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@ -1,7 +1,7 @@
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/*
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* SyncLink Multiprotocol Serial Adapter Driver
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*
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* $Id: synclink.h,v 3.13 2006/05/23 18:25:06 paulkf Exp $
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* $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $
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*
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* Copyright (C) 1998-2000 by Microgate Corporation
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*
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@ -124,6 +124,8 @@
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#define MGSL_MODE_ASYNC 1
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#define MGSL_MODE_HDLC 2
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#define MGSL_MODE_MONOSYNC 3
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#define MGSL_MODE_BISYNC 4
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#define MGSL_MODE_RAW 6
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#define MGSL_BUS_TYPE_ISA 1
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