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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring register
Before reading ring register, set FORCE_WAKE bit to prevent GT core power down to low power state, otherwise we may read stale values. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: added a udelay which seemed to do the trick on my SNB] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Zou Nan hai
Chris Wilson
parent
527f9e907c
commit
cae5852dca
@ -876,6 +876,67 @@ enum intel_chip_family {
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CHIP_I965 = 0x08,
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CHIP_I965 = 0x08,
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};
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};
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#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
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#define IS_I830(dev) ((dev)->pci_device == 0x3577)
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
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#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
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#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
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#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
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#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
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#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
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#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
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#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
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#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
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#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
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#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
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#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
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#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
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#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
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#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
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#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
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#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
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#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
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#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
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IS_I915GM(dev)))
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#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
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#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
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#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
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#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
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#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
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#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
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/* dsparb controlled by hw only */
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#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
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#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
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#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
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#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
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#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
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#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
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#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
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#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
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#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
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#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
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extern struct drm_ioctl_desc i915_ioctls[];
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extern struct drm_ioctl_desc i915_ioctls[];
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extern int i915_max_ioctl;
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extern int i915_max_ioctl;
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extern unsigned int i915_fbpercrtc;
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extern unsigned int i915_fbpercrtc;
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@ -1174,6 +1235,23 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
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LOCK_TEST_WITH_RETURN(dev, file_priv); \
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LOCK_TEST_WITH_RETURN(dev, file_priv); \
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} while (0)
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} while (0)
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#define I915_READ(reg) i915_read(dev_priv, (reg), 4)
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#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4)
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#define I915_READ16(reg) i915_read(dev_priv, (reg), 2)
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#define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2)
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#define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
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#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
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#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
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#define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
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#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
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#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
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#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
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#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len)
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static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len)
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{
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{
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u64 val = 0;
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u64 val = 0;
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@ -1197,6 +1275,23 @@ static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len)
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return val;
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return val;
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}
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}
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/* On SNB platform, before reading ring registers forcewake bit
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* must be set to prevent GT core from power down and stale values being
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* returned.
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*/
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static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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if (IS_GEN6(dev_priv->dev)) {
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I915_WRITE_NOTRACE(FORCEWAKE, 1);
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POSTING_READ(FORCEWAKE);
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/* XXX How long do we really need to wait here?
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* Will different registers/engines require different periods?
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*/
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udelay(100);
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}
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return I915_READ(reg);
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}
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static inline void
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static inline void
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i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
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i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
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{
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{
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@ -1218,24 +1313,6 @@ i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
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}
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}
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}
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}
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#define I915_READ(reg) i915_read(dev_priv, (reg), 4)
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#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4)
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#define I915_READ16(reg) i915_read(dev_priv, (reg), 2)
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#define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2)
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#define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
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#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
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#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
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#define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
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#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
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#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
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#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
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#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define BEGIN_LP_RING(n) \
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#define BEGIN_LP_RING(n) \
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intel_ring_begin(&dev_priv->render_ring, (n))
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intel_ring_begin(&dev_priv->render_ring, (n))
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@ -1266,67 +1343,4 @@ i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
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#define I915_GEM_HWS_INDEX 0x20
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#define I915_GEM_HWS_INDEX 0x20
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#define I915_BREADCRUMB_INDEX 0x21
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#define I915_BREADCRUMB_INDEX 0x21
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#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
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#define IS_I830(dev) ((dev)->pci_device == 0x3577)
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
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#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
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#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
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#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
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#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
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#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
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#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
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#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
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#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
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#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
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#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
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#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
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#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
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#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
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#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
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#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
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#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
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#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
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#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
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IS_I915GM(dev)))
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#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
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#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
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#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
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#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
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#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
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#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
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/* dsparb controlled by hw only */
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#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
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#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
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#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
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#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
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#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
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#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
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#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
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#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
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#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
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#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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#endif
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#endif
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@ -3077,4 +3077,5 @@
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#define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
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#define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
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#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
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#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
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#define FORCEWAKE 0xA18C
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#endif /* _I915_REG_H_ */
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#endif /* _I915_REG_H_ */
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@ -708,7 +708,7 @@ static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
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int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
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int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
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{
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{
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struct drm_device *dev = ring->dev;
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long end;
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unsigned long end;
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u32 head;
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u32 head;
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@ -7,13 +7,18 @@ struct intel_hw_status_page {
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struct drm_gem_object *obj;
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struct drm_gem_object *obj;
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};
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};
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
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#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
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#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
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#define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
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#define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
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#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
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#define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base))
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#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
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struct drm_i915_gem_execbuffer2;
|
struct drm_i915_gem_execbuffer2;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user