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drm/i915: Fix includes and local vars order

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Removed duplicate include and fixed comment > 80 chars.

v2: Added newline after system include and between functions

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200522131843.20477-1-stanislav.lisovskiy@intel.com
This commit is contained in:
Stanislav Lisovskiy 2020-05-22 16:18:43 +03:00 committed by Chris Wilson
parent b975abbd38
commit cac91e671a
6 changed files with 31 additions and 25 deletions
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46
drivers/gpu/drm/i915/display/intel_bw.c
View File

@ -5,13 +5,12 @@
#include <drm/drm_atomic_state_helper.h>
#include "intel_bw.h"
#include "intel_pm.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
#include "intel_atomic.h"
#include "intel_pm.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sideband.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@ -352,6 +351,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
return data_rate;
}
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state)
{
@ -431,13 +431,13 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int i;
struct intel_bw_state *new_bw_state = NULL;
struct intel_bw_state *old_bw_state = NULL;
const struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
int max_bw = 0;
int slice_id;
struct intel_bw_state *new_bw_state = NULL;
struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
enum plane_id plane_id;
@ -463,14 +463,17 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
/*
* FIXME: To calculate that more properly we probably need to
* to split per plane data_rate into data_rate_y and data_rate_uv
* for multiplanar formats in order not to get accounted those twice
* if they happen to reside on different slices.
* However for pre-icl this would work anyway because we have only single
* slice and for icl+ uv plane has non-zero data rate.
* So in worst case those calculation are a bit pessimistic, which
* shouldn't pose any significant problem anyway.
* FIXME: To calculate that more properly we probably
* need to to split per plane data_rate into data_rate_y
* and data_rate_uv for multiplanar formats in order not
* to get accounted those twice if they happen to reside
* on different slices.
* However for pre-icl this would work anyway because
* we have only single slice and for icl+ uv plane has
* non-zero data rate.
* So in worst case those calculation are a bit
* pessimistic, which shouldn't pose any significant
* problem anyway.
*/
for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
crtc_bw->used_bw[slice_id] += data_rate;
@ -478,11 +481,12 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
for_each_dbuf_slice(slice_id) {
/*
* Current experimental observations show that contrary to BSpec
* we get underruns once we exceed 64 * CDCLK for slices in total.
* As a temporary measure in order not to keep CDCLK bumped up all the
* time we calculate CDCLK according to this formula for overall bw
* consumed by slices.
* Current experimental observations show that contrary
* to BSpec we get underruns once we exceed 64 * CDCLK
* for slices in total.
* As a temporary measure in order not to keep CDCLK
* bumped up all the time we calculate CDCLK according
* to this formula for overall bw consumed by slices.
*/
max_bw += crtc_bw->used_bw[slice_id];
}

2
drivers/gpu/drm/i915/display/intel_bw.h
View File

@ -9,8 +9,8 @@
#include <drm/drm_atomic.h>
#include "intel_display.h"
#include "intel_global_state.h"
#include "intel_display_power.h"
#include "intel_global_state.h"
struct drm_i915_private;
struct intel_atomic_state;

3
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -22,11 +22,12 @@
*/
#include <linux/time.h>
#include "intel_atomic.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
#include "intel_bw.h"
/**
* DOC: CDCLK / RAWCLK

1
drivers/gpu/drm/i915/display/intel_cdclk.h
View File

@ -7,6 +7,7 @@
#define __INTEL_CDCLK_H__
#include <linux/types.h>
#include "i915_drv.h"
#include "intel_display.h"
#include "intel_global_state.h"

2
drivers/gpu/drm/i915/intel_pm.c
View File

@ -33,6 +33,7 @@
#include <drm/drm_plane_helper.h>
#include "display/intel_atomic.h"
#include "display/intel_bw.h"
#include "display/intel_display_types.h"
#include "display/intel_fbc.h"
#include "display/intel_sprite.h"
@ -43,7 +44,6 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"

2
drivers/gpu/drm/i915/intel_pm.h
View File

@ -8,10 +8,10 @@
#include <linux/types.h>
#include "display/intel_bw.h"
#include "display/intel_global_state.h"
#include "i915_reg.h"
#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;