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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 15:36:39 +07:00
drm/nouveau/pm: improve memtiming mappings
Improvements: - Fix bug in switch statement - Add parts of 0x10022c, 0x10023c - Clean up 0x100234 - Comment out assumption in 0x100228 until verified Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -651,6 +651,7 @@ nouveau_mem_gart_init(struct drm_device *dev)
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void
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nouveau_mem_timing_init(struct drm_device *dev)
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{
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/* cards < NVC0 only */
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
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struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
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@ -717,14 +718,14 @@ nouveau_mem_timing_init(struct drm_device *dev)
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tUNK_19 = 1;
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tUNK_20 = 0;
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tUNK_21 = 0;
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switch (min(recordlen, 21)) {
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case 21:
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switch (min(recordlen, 22)) {
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case 22:
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tUNK_21 = entry[21];
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case 20:
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case 21:
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tUNK_20 = entry[20];
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case 19:
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case 20:
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tUNK_19 = entry[19];
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case 18:
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case 19:
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tUNK_18 = entry[18];
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default:
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tUNK_0 = entry[0];
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@ -754,24 +755,30 @@ nouveau_mem_timing_init(struct drm_device *dev)
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timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
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if(recordlen > 19) {
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timing->reg_100228 += (tUNK_19 - 1) << 24;
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} else {
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}/* I cannot back-up this else-statement right now
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else {
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timing->reg_100228 += tUNK_12 << 24;
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}
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}*/
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/* XXX: reg_10022c */
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timing->reg_10022c = tUNK_2 - 1;
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timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
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tUNK_13 << 8 | tUNK_13);
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/* XXX: +6? */
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timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
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if(tUNK_10 > tUNK_11) {
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timing->reg_100234 += tUNK_10 << 16;
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} else {
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timing->reg_100234 += tUNK_11 << 16;
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timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
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/* XXX; reg_100238, reg_10023c
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* reg: 0x00??????
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* reg_10023c:
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* 0 for pre-NV50 cards
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* 0x????0202 for NV50+ cards (empirical evidence) */
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if(dev_priv->card_type >= NV_50) {
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timing->reg_10023c = 0x202;
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}
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/* XXX; reg_100238, reg_10023c */
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NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
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timing->reg_100220, timing->reg_100224,
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timing->reg_100228, timing->reg_10022c);
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