mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 14:36:41 +07:00
bnx2x: 57712 parity handling
- Added support for a parity error handling for a 57712 chip. - Changed the parity recovery scheme from per-chip to per-engine. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
This commit is contained in:
Vladislav Zolotarov
David S. Miller
parent
619c5cb688
commit
c9ee920624
@ -733,7 +733,6 @@ struct bnx2x_common {
|
||||
|
||||
#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
|
||||
#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
|
||||
#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
|
||||
#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
|
||||
(CHIP_REV_SHIFT + 1)) \
|
||||
<< CHIP_REV_SHIFT)
|
||||
@ -986,11 +985,13 @@ struct hw_context {
|
||||
/* forward */
|
||||
struct bnx2x_ilt;
|
||||
|
||||
typedef enum {
|
||||
|
||||
enum bnx2x_recovery_state {
|
||||
BNX2X_RECOVERY_DONE,
|
||||
BNX2X_RECOVERY_INIT,
|
||||
BNX2X_RECOVERY_WAIT,
|
||||
} bnx2x_recovery_state_t;
|
||||
BNX2X_RECOVERY_FAILED
|
||||
};
|
||||
|
||||
/*
|
||||
* Event queue (EQ or event ring) MC hsi
|
||||
@ -1076,7 +1077,7 @@ struct bnx2x {
|
||||
const struct iro *iro_arr;
|
||||
#define IRO (bp->iro_arr)
|
||||
|
||||
bnx2x_recovery_state_t recovery_state;
|
||||
enum bnx2x_recovery_state recovery_state;
|
||||
int is_leader;
|
||||
struct msix_entry *msix_table;
|
||||
|
||||
@ -1800,12 +1801,14 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
|
||||
(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
|
||||
AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
|
||||
#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
|
||||
AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
|
||||
#define HW_INTERRUT_ASSERT_SET_1 \
|
||||
(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
|
||||
@ -1818,17 +1821,22 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
|
||||
AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
|
||||
#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
|
||||
#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
|
||||
AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
|
||||
#define HW_INTERRUT_ASSERT_SET_2 \
|
||||
(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
|
||||
AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
|
||||
@ -1840,6 +1848,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
|
||||
AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
|
||||
AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
|
||||
AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
|
||||
|
||||
|
||||
@ -1918,13 +1918,23 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||
int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
|
||||
{
|
||||
int i;
|
||||
bool global = false;
|
||||
|
||||
if (bp->state == BNX2X_STATE_CLOSED) {
|
||||
/* Interface has been removed - nothing to recover */
|
||||
if ((bp->state == BNX2X_STATE_CLOSED) ||
|
||||
(bp->state == BNX2X_STATE_ERROR)) {
|
||||
/* We can get here if the driver has been unloaded
|
||||
* during parity error recovery and is either waiting for a
|
||||
* leader to complete or for other functions to unload and
|
||||
* then ifdown has been issued. In this case we want to
|
||||
* unload and let other functions to complete a recovery
|
||||
* process.
|
||||
*/
|
||||
bp->recovery_state = BNX2X_RECOVERY_DONE;
|
||||
bp->is_leader = 0;
|
||||
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
|
||||
smp_wmb();
|
||||
bnx2x_release_leader_lock(bp);
|
||||
smp_mb();
|
||||
|
||||
DP(NETIF_MSG_HW, "Releasing a leadership...\n");
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -1953,11 +1963,27 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
|
||||
if (unload_mode != UNLOAD_RECOVERY)
|
||||
bnx2x_chip_cleanup(bp, unload_mode);
|
||||
else {
|
||||
/* Disable HW interrupts, NAPI and Tx */
|
||||
/* Send the UNLOAD_REQUEST to the MCP */
|
||||
bnx2x_send_unload_req(bp, unload_mode);
|
||||
|
||||
/*
|
||||
* Prevent transactions to host from the functions on the
|
||||
* engine that doesn't reset global blocks in case of global
|
||||
* attention once gloabl blocks are reset and gates are opened
|
||||
* (the engine which leader will perform the recovery
|
||||
* last).
|
||||
*/
|
||||
if (!CHIP_IS_E1x(bp))
|
||||
bnx2x_pf_disable(bp);
|
||||
|
||||
/* Disable HW interrupts, NAPI */
|
||||
bnx2x_netif_stop(bp, 1);
|
||||
|
||||
/* Release IRQs */
|
||||
bnx2x_free_irq(bp);
|
||||
|
||||
/* Report UNLOAD_DONE to MCP */
|
||||
bnx2x_send_unload_done(bp);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1977,17 +2003,24 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
|
||||
|
||||
bp->state = BNX2X_STATE_CLOSED;
|
||||
|
||||
/* Check if there are pending parity attentions. If there are - set
|
||||
* RECOVERY_IN_PROGRESS.
|
||||
*/
|
||||
if (bnx2x_chk_parity_attn(bp, &global, false)) {
|
||||
bnx2x_set_reset_in_progress(bp);
|
||||
|
||||
/* Set RESET_IS_GLOBAL if needed */
|
||||
if (global)
|
||||
bnx2x_set_reset_global(bp);
|
||||
}
|
||||
|
||||
|
||||
/* The last driver must disable a "close the gate" if there is no
|
||||
* parity attention or "process kill" pending.
|
||||
*/
|
||||
if ((!bnx2x_dec_load_cnt(bp)) && (!bnx2x_chk_parity_attn(bp)) &&
|
||||
bnx2x_reset_is_done(bp))
|
||||
if (!bnx2x_dec_load_cnt(bp) && bnx2x_reset_is_done(bp, BP_PATH(bp)))
|
||||
bnx2x_disable_close_the_gate(bp);
|
||||
|
||||
/* Reset MCP mail box sequence if there is on going recovery */
|
||||
if (unload_mode == UNLOAD_RECOVERY)
|
||||
bp->fw_seq = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -181,6 +181,9 @@ void bnx2x_drv_pulse(struct bnx2x *bp);
|
||||
void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
|
||||
u16 index, u8 op, u8 update);
|
||||
|
||||
/* Disable transactions from chip to host */
|
||||
void bnx2x_pf_disable(struct bnx2x *bp);
|
||||
|
||||
/**
|
||||
* bnx2x__link_status_update - handles link status change.
|
||||
*
|
||||
@ -320,6 +323,13 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
|
||||
*/
|
||||
int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
|
||||
|
||||
/**
|
||||
* bnx2x_release_leader_lock - release recovery leader lock
|
||||
*
|
||||
* @bp: driver handle
|
||||
*/
|
||||
int bnx2x_release_leader_lock(struct bnx2x *bp);
|
||||
|
||||
/**
|
||||
* bnx2x_set_eth_mac - configure eth MAC address in the HW
|
||||
*
|
||||
@ -370,8 +380,10 @@ void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
|
||||
/* Parity errors related */
|
||||
void bnx2x_inc_load_cnt(struct bnx2x *bp);
|
||||
u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
|
||||
bool bnx2x_chk_parity_attn(struct bnx2x *bp);
|
||||
bool bnx2x_reset_is_done(struct bnx2x *bp);
|
||||
bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
|
||||
bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
|
||||
void bnx2x_set_reset_in_progress(struct bnx2x *bp);
|
||||
void bnx2x_set_reset_global(struct bnx2x *bp);
|
||||
void bnx2x_disable_close_the_gate(struct bnx2x *bp);
|
||||
|
||||
/**
|
||||
|
||||
@ -634,8 +634,7 @@ static void bnx2x_get_regs(struct net_device *dev,
|
||||
}
|
||||
/* Re-enable parity attentions */
|
||||
bnx2x_clear_blocks_parity(bp);
|
||||
if (CHIP_PARITY_ENABLED(bp))
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
}
|
||||
|
||||
static void bnx2x_get_drvinfo(struct net_device *dev,
|
||||
|
||||
@ -377,12 +377,15 @@ static const struct {
|
||||
BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
|
||||
BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
|
||||
BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0),
|
||||
BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xffff),
|
||||
BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
|
||||
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
|
||||
BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
|
||||
BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
|
||||
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
|
||||
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
|
||||
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
|
||||
{0xf, 0xf, 0xf}, "UPB"},
|
||||
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
|
||||
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
|
||||
@ -394,10 +397,16 @@ static const struct {
|
||||
BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
|
||||
BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
|
||||
BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
|
||||
BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffffff),
|
||||
BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f),
|
||||
BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff),
|
||||
BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
|
||||
BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -804,10 +804,12 @@
|
||||
/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
|
||||
#define DORQ_REG_SHRT_CMHEAD 0x170054
|
||||
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
|
||||
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
|
||||
#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
|
||||
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
|
||||
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
|
||||
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
|
||||
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
|
||||
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
|
||||
#define HC_REG_AGG_INT_0 0x108050
|
||||
#define HC_REG_AGG_INT_1 0x108054
|
||||
#define HC_REG_ATTN_BIT 0x108120
|
||||
@ -846,6 +848,7 @@
|
||||
#define HC_REG_VQID_0 0x108008
|
||||
#define HC_REG_VQID_1 0x10800c
|
||||
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
|
||||
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
|
||||
#define IGU_REG_ATTENTION_ACK_BITS 0x130108
|
||||
/* [R 4] Debug: attn_fsm */
|
||||
#define IGU_REG_ATTN_FSM 0x130054
|
||||
@ -1876,11 +1879,21 @@
|
||||
/* [R 32] Interrupt register #0 read */
|
||||
#define NIG_REG_NIG_INT_STS_0 0x103b0
|
||||
#define NIG_REG_NIG_INT_STS_1 0x103c0
|
||||
/* [R 32] Legacy E1 and E1H location for parity error mask register. */
|
||||
#define NIG_REG_NIG_PRTY_MASK 0x103dc
|
||||
/* [RW 32] Parity mask register #0 read/write */
|
||||
#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
|
||||
#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
|
||||
/* [R 32] Legacy E1 and E1H location for parity error status register. */
|
||||
#define NIG_REG_NIG_PRTY_STS 0x103d0
|
||||
/* [R 32] Parity register #0 read */
|
||||
#define NIG_REG_NIG_PRTY_STS_0 0x183bc
|
||||
#define NIG_REG_NIG_PRTY_STS_1 0x183cc
|
||||
/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
|
||||
#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
|
||||
#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
|
||||
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
|
||||
* Ethernet header. */
|
||||
#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
|
||||
@ -4322,6 +4335,8 @@
|
||||
#define UCM_REG_UCM_INT_MASK 0xe01d4
|
||||
/* [R 11] Interrupt register #0 read */
|
||||
#define UCM_REG_UCM_INT_STS 0xe01c8
|
||||
/* [RW 27] Parity mask register #0 read/write */
|
||||
#define UCM_REG_UCM_PRTY_MASK 0xe01e4
|
||||
/* [R 27] Parity register #0 read */
|
||||
#define UCM_REG_UCM_PRTY_STS 0xe01d8
|
||||
/* [RC 27] Parity register #0 read clear */
|
||||
@ -4843,8 +4858,13 @@
|
||||
#define XCM_REG_XCM_INT_MASK 0x202b4
|
||||
/* [R 14] Interrupt register #0 read */
|
||||
#define XCM_REG_XCM_INT_STS 0x202a8
|
||||
/* [RW 30] Parity mask register #0 read/write */
|
||||
#define XCM_REG_XCM_PRTY_MASK 0x202c4
|
||||
/* [R 30] Parity register #0 read */
|
||||
#define XCM_REG_XCM_PRTY_STS 0x202b8
|
||||
/* [RC 30] Parity register #0 read clear */
|
||||
#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
|
||||
|
||||
/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
|
||||
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
|
||||
Is used to determine the number of the AG context REG-pairs written back;
|
||||
@ -5284,9 +5304,12 @@
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
|
||||
#define MISC_REGISTERS_RESET_REG_2_SET 0x594
|
||||
#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
|
||||
@ -5315,71 +5338,82 @@
|
||||
#define HW_LOCK_MAX_RESOURCE_VALUE 31
|
||||
#define HW_LOCK_RESOURCE_GPIO 1
|
||||
#define HW_LOCK_RESOURCE_MDIO 0
|
||||
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
|
||||
#define HW_LOCK_RESOURCE_RESERVED_08 8
|
||||
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
|
||||
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
|
||||
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
|
||||
#define HW_LOCK_RESOURCE_SPIO 2
|
||||
#define HW_LOCK_RESOURCE_UNDI 5
|
||||
#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
|
||||
#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
|
||||
#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
|
||||
#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
|
||||
#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
|
||||
#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
|
||||
#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
|
||||
#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
|
||||
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
|
||||
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
|
||||
#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30)
|
||||
#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
|
||||
#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
|
||||
#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
|
||||
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
|
||||
#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
|
||||
#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
|
||||
#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
|
||||
#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
|
||||
#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
|
||||
#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
|
||||
#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
|
||||
#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
|
||||
#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
|
||||
#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
|
||||
#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
|
||||
#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
|
||||
#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
|
||||
#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
|
||||
#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
|
||||
#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
|
||||
#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
|
||||
#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
|
||||
#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
|
||||
#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
|
||||
#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
|
||||
#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
|
||||
#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
|
||||
#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
|
||||
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
|
||||
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
|
||||
#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
|
||||
#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
|
||||
#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
|
||||
#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
|
||||
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
|
||||
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
|
||||
#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
|
||||
#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
|
||||
#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
|
||||
#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
|
||||
#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
|
||||
#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
|
||||
#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
|
||||
#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
|
||||
#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
|
||||
#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
|
||||
#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
|
||||
#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
|
||||
#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
|
||||
#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
|
||||
#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
|
||||
#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
|
||||
#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
|
||||
#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
|
||||
#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
|
||||
#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
|
||||
#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
|
||||
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
|
||||
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
|
||||
|
||||
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
|
||||
|
||||
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
|
||||
#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
|
||||
#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
|
||||
|
||||
#define RESERVED_GENERAL_ATTENTION_BIT_6 6
|
||||
|
||||
Loading…
Reference in New Issue
Block a user