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[ARM] pxa: correct SSCR0_SCR to support multiple SoCs

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The previous definitions of SSCR0_SCR and SSCR0_SerClkDiv() prevented
them being used simultaneously when supporting multiple PXA SoCs, esp.
in drivers/spi/pxa2xx_spi.c, make them correct.

The change from SSCR0_SerClkDiv(2) to SSCR0_SCR(2), will make the result
a little bit different in pxa2xx_spi_probe(), however, since that's only
used as a default initialization value, it's acceptable.

Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This commit is contained in:
Eric Miao 2010-03-16 16:48:01 +08:00
parent 793ffb9ed3
commit c9840daa70
2 changed files with 8 additions and 15 deletions
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9
arch/arm/mach-pxa/include/mach/regs-ssp.h
View File

@ -33,14 +33,7 @@
#define SSCR0_National (0x2 << 4) /* National Microwire */ #define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */ #define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
#if defined(CONFIG_PXA25x)
#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#endif
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_EDSS (1 << 20) /* Extended data size select */ #define SSCR0_EDSS (1 << 20) /* Extended data size select */

14
drivers/spi/pxa2xx_spi.c
View File

@ -1318,14 +1318,14 @@ static int setup(struct spi_device *spi)
/* NOTE: PXA25x_SSP _could_ use external clocking ... */ /* NOTE: PXA25x_SSP _could_ use external clocking ... */
if (drv_data->ssp_type != PXA25x_SSP) if (drv_data->ssp_type != PXA25x_SSP)
dev_dbg(&spi->dev, "%ld Hz actual, %s\n", dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
clk_get_rate(ssp->clk) clk_get_rate(ssp->clk)
/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
chip->enable_dma ? "DMA" : "PIO"); chip->enable_dma ? "DMA" : "PIO");
else else
dev_dbg(&spi->dev, "%ld Hz actual, %s\n", dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
clk_get_rate(ssp->clk) / 2 clk_get_rate(ssp->clk) / 2
/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
chip->enable_dma ? "DMA" : "PIO"); chip->enable_dma ? "DMA" : "PIO");
if (spi->bits_per_word <= 8) { if (spi->bits_per_word <= 8) {
chip->n_bytes = 1; chip->n_bytes = 1;
@ -1558,7 +1558,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
SSCR1_TxTresh(TX_THRESH_DFLT), SSCR1_TxTresh(TX_THRESH_DFLT),
drv_data->ioaddr); drv_data->ioaddr);
write_SSCR0(SSCR0_SerClkDiv(2) write_SSCR0(SSCR0_SCR(2)
| SSCR0_Motorola | SSCR0_Motorola
| SSCR0_DataSize(8), | SSCR0_DataSize(8),
drv_data->ioaddr); drv_data->ioaddr);