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ixgbe: Add check for FW veto bit
The driver will now honor the MNG FW veto bit in blocking link resets. This patch will affect x520 and x540 systems. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2013 Intel Corporation.
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Copyright(c) 1999 - 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -233,6 +233,10 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
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{
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s32 ret_val = 0;
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/* Blocked by MNG FW so bail */
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if (ixgbe_check_reset_blocked(hw))
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goto out;
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/* We only need to get the lock if:
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* - We didn't do it already (in the read part of a read-modify-write)
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* - LESM is enabled.
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@ -247,6 +251,7 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
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ret_val = ixgbe_reset_pipeline_82599(hw);
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out:
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/* Free the SW/FW semaphore as we either grabbed it here or
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* already had it when this function was called.
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*/
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@ -591,6 +596,10 @@ static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
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{
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u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
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/* Blocked by MNG FW so bail */
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if (ixgbe_check_reset_blocked(hw))
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return;
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/* Disable tx laser; allow 100us to go dark per spec */
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esdp_reg |= IXGBE_ESDP_SDP3;
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IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
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@ -631,6 +640,10 @@ static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
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**/
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static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
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{
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/* Blocked by MNG FW so bail */
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if (ixgbe_check_reset_blocked(hw))
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return;
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if (hw->mac.autotry_restart) {
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ixgbe_disable_tx_laser_multispeed_fiber(hw);
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ixgbe_enable_tx_laser_multispeed_fiber(hw);
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2013 Intel Corporation.
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Copyright(c) 1999 - 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -97,6 +97,32 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
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return status;
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}
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/**
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* ixgbe_check_reset_blocked - check status of MNG FW veto bit
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* @hw: pointer to the hardware structure
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*
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* This function checks the MMNGC.MNG_VETO bit to see if there are
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* any constraints on link from manageability. For MAC's that don't
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* have this bit just return false since the link can not be blocked
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* via this method.
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**/
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s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
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{
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u32 mmngc;
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/* If we don't have this bit, it can't be blocking */
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if (hw->mac.type == ixgbe_mac_82598EB)
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return false;
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mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
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if (mmngc & IXGBE_MMNGC_MNG_VETO) {
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hw_dbg(hw, "MNG_VETO bit detected.\n");
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return true;
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}
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return false;
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}
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/**
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* ixgbe_get_phy_id - Get the phy type
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* @hw: pointer to hardware structure
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@ -172,6 +198,10 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
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(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
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goto out;
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/* Blocked by MNG FW so bail */
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if (ixgbe_check_reset_blocked(hw))
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goto out;
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/*
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* Perform soft PHY reset to the PHY_XS.
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* This will cause a soft reset to the PHY
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@ -476,6 +506,10 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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autoneg_reg);
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}
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/* Blocked by MNG FW so don't reset PHY */
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if (ixgbe_check_reset_blocked(hw))
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return status;
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/* Restart PHY autonegotiation and wait for completion */
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hw->phy.ops.read_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, &autoneg_reg);
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@ -682,6 +716,10 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
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autoneg_reg);
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}
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/* Blocked by MNG FW so don't reset PHY */
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if (ixgbe_check_reset_blocked(hw))
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return status;
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/* Restart PHY autonegotiation and wait for completion */
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hw->phy.ops.read_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, &autoneg_reg);
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@ -759,6 +797,10 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
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s32 ret_val = 0;
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u32 i;
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/* Blocked by MNG FW so bail */
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if (ixgbe_check_reset_blocked(hw))
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goto out;
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hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
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/* reset the PHY and poll for completion */
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2013 Intel Corporation.
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Copyright(c) 1999 - 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -131,6 +131,7 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *autoneg);
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s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
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/* PHY specific */
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s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2013 Intel Corporation.
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Copyright(c) 1999 - 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -1610,6 +1610,9 @@ enum {
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#define IXGBE_MACC_FS 0x00040000
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#define IXGBE_MAC_RX2TX_LPBK 0x00000002
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/* Veto Bit definiton */
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#define IXGBE_MMNGC_MNG_VETO 0x00000001
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/* LINKS Bit Masks */
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#define IXGBE_LINKS_KX_AN_COMP 0x80000000
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#define IXGBE_LINKS_UP 0x40000000
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