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RISC-V: sfence.vma orderes the instruction cache

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This is just a comment change, but it's one that bit me on the mailing
list.  It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering.  This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.

CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Palmer Dabbelt 2017-11-28 14:06:17 -08:00
parent 21db403660
commit c901e45a99
1 changed files with 4 additions and 1 deletions
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5
arch/riscv/include/asm/tlbflush.h
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@ -17,7 +17,10 @@
#ifdef CONFIG_MMU
/* Flush entire local TLB */
/*
* Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
* cache as well, so a 'fence.i' is not necessary.
*/
static inline void local_flush_tlb_all(void)
{
__asm__ __volatile__ ("sfence.vma" : : : "memory");