mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 21:26:42 +07:00
Merge commit 'v2.6.38-rc8' into x86/asm
Merge reason: Update with the latest fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
commit
c8b44163b7
1
.gitignore
vendored
1
.gitignore
vendored
@ -28,6 +28,7 @@ modules.builtin
|
||||
*.gz
|
||||
*.bz2
|
||||
*.lzma
|
||||
*.xz
|
||||
*.lzo
|
||||
*.patch
|
||||
*.gcno
|
||||
|
@ -73,8 +73,8 @@
|
||||
services.
|
||||
</para>
|
||||
<para>
|
||||
The core of every DRM driver is struct drm_device. Drivers
|
||||
will typically statically initialize a drm_device structure,
|
||||
The core of every DRM driver is struct drm_driver. Drivers
|
||||
will typically statically initialize a drm_driver structure,
|
||||
then pass it to drm_init() at load time.
|
||||
</para>
|
||||
|
||||
@ -84,7 +84,7 @@
|
||||
<title>Driver initialization</title>
|
||||
<para>
|
||||
Before calling the DRM initialization routines, the driver must
|
||||
first create and fill out a struct drm_device structure.
|
||||
first create and fill out a struct drm_driver structure.
|
||||
</para>
|
||||
<programlisting>
|
||||
static struct drm_driver driver = {
|
||||
|
@ -82,6 +82,11 @@
|
||||
</sect1>
|
||||
</chapter>
|
||||
|
||||
<chapter id="fs_events">
|
||||
<title>Events based on file descriptors</title>
|
||||
!Efs/eventfd.c
|
||||
</chapter>
|
||||
|
||||
<chapter id="sysfs">
|
||||
<title>The Filesystem for Exporting Kernel Objects</title>
|
||||
!Efs/sysfs/file.c
|
||||
|
@ -13,7 +13,6 @@ Table of Contents
|
||||
|
||||
I - Introduction
|
||||
1) Entry point for arch/powerpc
|
||||
2) Board support
|
||||
|
||||
II - The DT block format
|
||||
1) Header
|
||||
@ -41,13 +40,6 @@ Table of Contents
|
||||
VI - System-on-a-chip devices and nodes
|
||||
1) Defining child nodes of an SOC
|
||||
2) Representing devices without a current OF specification
|
||||
a) PHY nodes
|
||||
b) Interrupt controllers
|
||||
c) 4xx/Axon EMAC ethernet nodes
|
||||
d) Xilinx IP cores
|
||||
e) USB EHCI controllers
|
||||
f) MDIO on GPIOs
|
||||
g) SPI busses
|
||||
|
||||
VII - Specifying interrupt information for devices
|
||||
1) interrupts property
|
||||
@ -123,7 +115,7 @@ Revision Information
|
||||
I - Introduction
|
||||
================
|
||||
|
||||
During the recent development of the Linux/ppc64 kernel, and more
|
||||
During the development of the Linux/ppc64 kernel, and more
|
||||
specifically, the addition of new platform types outside of the old
|
||||
IBM pSeries/iSeries pair, it was decided to enforce some strict rules
|
||||
regarding the kernel entry and bootloader <-> kernel interfaces, in
|
||||
@ -146,7 +138,7 @@ section III, but, for example, the kernel does not require you to
|
||||
create a node for every PCI device in the system. It is a requirement
|
||||
to have a node for PCI host bridges in order to provide interrupt
|
||||
routing informations and memory/IO ranges, among others. It is also
|
||||
recommended to define nodes for on chip devices and other busses that
|
||||
recommended to define nodes for on chip devices and other buses that
|
||||
don't specifically fit in an existing OF specification. This creates a
|
||||
great flexibility in the way the kernel can then probe those and match
|
||||
drivers to device, without having to hard code all sorts of tables. It
|
||||
@ -158,7 +150,7 @@ it with special cases.
|
||||
1) Entry point for arch/powerpc
|
||||
-------------------------------
|
||||
|
||||
There is one and one single entry point to the kernel, at the start
|
||||
There is one single entry point to the kernel, at the start
|
||||
of the kernel image. That entry point supports two calling
|
||||
conventions:
|
||||
|
||||
@ -210,12 +202,6 @@ it with special cases.
|
||||
with all CPUs. The way to do that with method b) will be
|
||||
described in a later revision of this document.
|
||||
|
||||
|
||||
2) Board support
|
||||
----------------
|
||||
|
||||
64-bit kernels:
|
||||
|
||||
Board supports (platforms) are not exclusive config options. An
|
||||
arbitrary set of board supports can be built in a single kernel
|
||||
image. The kernel will "know" what set of functions to use for a
|
||||
@ -234,48 +220,11 @@ it with special cases.
|
||||
containing the various callbacks that the generic code will
|
||||
use to get to your platform specific code
|
||||
|
||||
c) Add a reference to your "ppc_md" structure in the
|
||||
"machines" table in arch/powerpc/kernel/setup_64.c if you are
|
||||
a 64-bit platform.
|
||||
|
||||
d) request and get assigned a platform number (see PLATFORM_*
|
||||
constants in arch/powerpc/include/asm/processor.h
|
||||
|
||||
32-bit embedded kernels:
|
||||
|
||||
Currently, board support is essentially an exclusive config option.
|
||||
The kernel is configured for a single platform. Part of the reason
|
||||
for this is to keep kernels on embedded systems small and efficient;
|
||||
part of this is due to the fact the code is already that way. In the
|
||||
future, a kernel may support multiple platforms, but only if the
|
||||
A kernel image may support multiple platforms, but only if the
|
||||
platforms feature the same core architecture. A single kernel build
|
||||
cannot support both configurations with Book E and configurations
|
||||
with classic Powerpc architectures.
|
||||
|
||||
32-bit embedded platforms that are moved into arch/powerpc using a
|
||||
flattened device tree should adopt the merged tree practice of
|
||||
setting ppc_md up dynamically, even though the kernel is currently
|
||||
built with support for only a single platform at a time. This allows
|
||||
unification of the setup code, and will make it easier to go to a
|
||||
multiple-platform-support model in the future.
|
||||
|
||||
NOTE: I believe the above will be true once Ben's done with the merge
|
||||
of the boot sequences.... someone speak up if this is wrong!
|
||||
|
||||
To add a 32-bit embedded platform support, follow the instructions
|
||||
for 64-bit platforms above, with the exception that the Kconfig
|
||||
option should be set up such that the kernel builds exclusively for
|
||||
the platform selected. The processor type for the platform should
|
||||
enable another config option to select the specific board
|
||||
supported.
|
||||
|
||||
NOTE: If Ben doesn't merge the setup files, may need to change this to
|
||||
point to setup_32.c
|
||||
|
||||
|
||||
I will describe later the boot process and various callbacks that
|
||||
your platform should implement.
|
||||
|
||||
|
||||
II - The DT block format
|
||||
========================
|
||||
@ -300,8 +249,8 @@ the block to RAM before passing it to the kernel.
|
||||
1) Header
|
||||
---------
|
||||
|
||||
The kernel is entered with r3 pointing to an area of memory that is
|
||||
roughly described in arch/powerpc/include/asm/prom.h by the structure
|
||||
The kernel is passed the physical address pointing to an area of memory
|
||||
that is roughly described in include/linux/of_fdt.h by the structure
|
||||
boot_param_header:
|
||||
|
||||
struct boot_param_header {
|
||||
@ -339,7 +288,7 @@ struct boot_param_header {
|
||||
All values in this header are in big endian format, the various
|
||||
fields in this header are defined more precisely below. All
|
||||
"offset" values are in bytes from the start of the header; that is
|
||||
from the value of r3.
|
||||
from the physical base address of the device tree block.
|
||||
|
||||
- magic
|
||||
|
||||
@ -437,7 +386,7 @@ struct boot_param_header {
|
||||
|
||||
|
||||
------------------------------
|
||||
r3 -> | struct boot_param_header |
|
||||
base -> | struct boot_param_header |
|
||||
------------------------------
|
||||
| (alignment gap) (*) |
|
||||
------------------------------
|
||||
@ -457,7 +406,7 @@ struct boot_param_header {
|
||||
-----> ------------------------------
|
||||
|
|
||||
|
|
||||
--- (r3 + totalsize)
|
||||
--- (base + totalsize)
|
||||
|
||||
(*) The alignment gaps are not necessarily present; their presence
|
||||
and size are dependent on the various alignment requirements of
|
||||
@ -500,7 +449,7 @@ the device-tree structure. It is typically used to represent "path" in
|
||||
the device-tree. More details about the actual format of these will be
|
||||
below.
|
||||
|
||||
The kernel powerpc generic code does not make any formal use of the
|
||||
The kernel generic code does not make any formal use of the
|
||||
unit address (though some board support code may do) so the only real
|
||||
requirement here for the unit address is to ensure uniqueness of
|
||||
the node unit name at a given level of the tree. Nodes with no notion
|
||||
@ -518,20 +467,21 @@ path to the root node is "/".
|
||||
|
||||
Every node which actually represents an actual device (that is, a node
|
||||
which isn't only a virtual "container" for more nodes, like "/cpus"
|
||||
is) is also required to have a "device_type" property indicating the
|
||||
type of node .
|
||||
is) is also required to have a "compatible" property indicating the
|
||||
specific hardware and an optional list of devices it is fully
|
||||
backwards compatible with.
|
||||
|
||||
Finally, every node that can be referenced from a property in another
|
||||
node is required to have a "linux,phandle" property. Real open
|
||||
firmware implementations provide a unique "phandle" value for every
|
||||
node that the "prom_init()" trampoline code turns into
|
||||
"linux,phandle" properties. However, this is made optional if the
|
||||
flattened device tree is used directly. An example of a node
|
||||
node is required to have either a "phandle" or a "linux,phandle"
|
||||
property. Real Open Firmware implementations provide a unique
|
||||
"phandle" value for every node that the "prom_init()" trampoline code
|
||||
turns into "linux,phandle" properties. However, this is made optional
|
||||
if the flattened device tree is used directly. An example of a node
|
||||
referencing another node via "phandle" is when laying out the
|
||||
interrupt tree which will be described in a further version of this
|
||||
document.
|
||||
|
||||
This "linux, phandle" property is a 32-bit value that uniquely
|
||||
The "phandle" property is a 32-bit value that uniquely
|
||||
identifies a node. You are free to use whatever values or system of
|
||||
values, internal pointers, or whatever to generate these, the only
|
||||
requirement is that every node for which you provide that property has
|
||||
@ -694,7 +644,7 @@ made of 3 cells, the bottom two containing the actual address itself
|
||||
while the top cell contains address space indication, flags, and pci
|
||||
bus & device numbers.
|
||||
|
||||
For busses that support dynamic allocation, it's the accepted practice
|
||||
For buses that support dynamic allocation, it's the accepted practice
|
||||
to then not provide the address in "reg" (keep it 0) though while
|
||||
providing a flag indicating the address is dynamically allocated, and
|
||||
then, to provide a separate "assigned-addresses" property that
|
||||
@ -711,7 +661,7 @@ prom_parse.c file of the recent kernels for your bus type.
|
||||
The "reg" property only defines addresses and sizes (if #size-cells is
|
||||
non-0) within a given bus. In order to translate addresses upward
|
||||
(that is into parent bus addresses, and possibly into CPU physical
|
||||
addresses), all busses must contain a "ranges" property. If the
|
||||
addresses), all buses must contain a "ranges" property. If the
|
||||
"ranges" property is missing at a given level, it's assumed that
|
||||
translation isn't possible, i.e., the registers are not visible on the
|
||||
parent bus. The format of the "ranges" property for a bus is a list
|
||||
@ -727,9 +677,9 @@ example, for a PCI host controller, that would be a CPU address. For a
|
||||
PCI<->ISA bridge, that would be a PCI address. It defines the base
|
||||
address in the parent bus where the beginning of that range is mapped.
|
||||
|
||||
For a new 64-bit powerpc board, I recommend either the 2/2 format or
|
||||
For new 64-bit board support, I recommend either the 2/2 format or
|
||||
Apple's 2/1 format which is slightly more compact since sizes usually
|
||||
fit in a single 32-bit word. New 32-bit powerpc boards should use a
|
||||
fit in a single 32-bit word. New 32-bit board support should use a
|
||||
1/1 format, unless the processor supports physical addresses greater
|
||||
than 32-bits, in which case a 2/1 format is recommended.
|
||||
|
||||
@ -754,7 +704,7 @@ of their actual names.
|
||||
While earlier users of Open Firmware like OldWorld macintoshes tended
|
||||
to use the actual device name for the "name" property, it's nowadays
|
||||
considered a good practice to use a name that is closer to the device
|
||||
class (often equal to device_type). For example, nowadays, ethernet
|
||||
class (often equal to device_type). For example, nowadays, Ethernet
|
||||
controllers are named "ethernet", an additional "model" property
|
||||
defining precisely the chip type/model, and "compatible" property
|
||||
defining the family in case a single driver can driver more than one
|
||||
@ -772,7 +722,7 @@ is present).
|
||||
4) Note about node and property names and character set
|
||||
-------------------------------------------------------
|
||||
|
||||
While open firmware provides more flexible usage of 8859-1, this
|
||||
While Open Firmware provides more flexible usage of 8859-1, this
|
||||
specification enforces more strict rules. Nodes and properties should
|
||||
be comprised only of ASCII characters 'a' to 'z', '0' to
|
||||
'9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
|
||||
@ -792,7 +742,7 @@ address which can extend beyond that limit.
|
||||
--------------------------------
|
||||
These are all that are currently required. However, it is strongly
|
||||
recommended that you expose PCI host bridges as documented in the
|
||||
PCI binding to open firmware, and your interrupt tree as documented
|
||||
PCI binding to Open Firmware, and your interrupt tree as documented
|
||||
in OF interrupt tree specification.
|
||||
|
||||
a) The root node
|
||||
@ -802,20 +752,12 @@ address which can extend beyond that limit.
|
||||
- model : this is your board name/model
|
||||
- #address-cells : address representation for "root" devices
|
||||
- #size-cells: the size representation for "root" devices
|
||||
- device_type : This property shouldn't be necessary. However, if
|
||||
you decide to create a device_type for your root node, make sure it
|
||||
is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
|
||||
one for 64-bit, or a CHRP-type machine for 32-bit as this will
|
||||
matched by the kernel this way.
|
||||
|
||||
Additionally, some recommended properties are:
|
||||
|
||||
- compatible : the board "family" generally finds its way here,
|
||||
for example, if you have 2 board models with a similar layout,
|
||||
that typically get driven by the same platform code in the
|
||||
kernel, you would use a different "model" property but put a
|
||||
value in "compatible". The kernel doesn't directly use that
|
||||
value but it is generally useful.
|
||||
kernel, you would specify the exact board model in the
|
||||
compatible property followed by an entry that represents the SoC
|
||||
model.
|
||||
|
||||
The root node is also generally where you add additional properties
|
||||
specific to your board like the serial number if any, that sort of
|
||||
@ -841,8 +783,11 @@ address which can extend beyond that limit.
|
||||
|
||||
So under /cpus, you are supposed to create a node for every CPU on
|
||||
the machine. There is no specific restriction on the name of the
|
||||
CPU, though It's common practice to call it PowerPC,<name>. For
|
||||
CPU, though it's common to call it <architecture>,<core>. For
|
||||
example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
|
||||
However, the Generic Names convention suggests that it would be
|
||||
better to simply use 'cpu' for each cpu node and use the compatible
|
||||
property to identify the specific cpu core.
|
||||
|
||||
Required properties:
|
||||
|
||||
@ -923,7 +868,7 @@ compatibility.
|
||||
|
||||
e) The /chosen node
|
||||
|
||||
This node is a bit "special". Normally, that's where open firmware
|
||||
This node is a bit "special". Normally, that's where Open Firmware
|
||||
puts some variable environment information, like the arguments, or
|
||||
the default input/output devices.
|
||||
|
||||
@ -940,11 +885,7 @@ compatibility.
|
||||
console device if any. Typically, if you have serial devices on
|
||||
your board, you may want to put the full path to the one set as
|
||||
the default console in the firmware here, for the kernel to pick
|
||||
it up as its own default console. If you look at the function
|
||||
set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
|
||||
that the kernel tries to find out the default console and has
|
||||
knowledge of various types like 8250 serial ports. You may want
|
||||
to extend this function to add your own.
|
||||
it up as its own default console.
|
||||
|
||||
Note that u-boot creates and fills in the chosen node for platforms
|
||||
that use it.
|
||||
@ -955,23 +896,23 @@ compatibility.
|
||||
|
||||
f) the /soc<SOCname> node
|
||||
|
||||
This node is used to represent a system-on-a-chip (SOC) and must be
|
||||
present if the processor is a SOC. The top-level soc node contains
|
||||
information that is global to all devices on the SOC. The node name
|
||||
should contain a unit address for the SOC, which is the base address
|
||||
of the memory-mapped register set for the SOC. The name of an soc
|
||||
This node is used to represent a system-on-a-chip (SoC) and must be
|
||||
present if the processor is a SoC. The top-level soc node contains
|
||||
information that is global to all devices on the SoC. The node name
|
||||
should contain a unit address for the SoC, which is the base address
|
||||
of the memory-mapped register set for the SoC. The name of an SoC
|
||||
node should start with "soc", and the remainder of the name should
|
||||
represent the part number for the soc. For example, the MPC8540's
|
||||
soc node would be called "soc8540".
|
||||
|
||||
Required properties:
|
||||
|
||||
- device_type : Should be "soc"
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
translation of SOC addresses for memory mapped SOC registers.
|
||||
- bus-frequency: Contains the bus frequency for the SOC node.
|
||||
translation of SoC addresses for memory mapped SoC registers.
|
||||
- bus-frequency: Contains the bus frequency for the SoC node.
|
||||
Typically, the value of this field is filled in by the boot
|
||||
loader.
|
||||
- compatible : Exact model of the SoC
|
||||
|
||||
|
||||
Recommended properties:
|
||||
@ -1155,12 +1096,13 @@ while all this has been defined and implemented.
|
||||
|
||||
- An example of code for iterating nodes & retrieving properties
|
||||
directly from the flattened tree format can be found in the kernel
|
||||
file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
|
||||
file drivers/of/fdt.c. Look at the of_scan_flat_dt() function,
|
||||
its usage in early_init_devtree(), and the corresponding various
|
||||
early_init_dt_scan_*() callbacks. That code can be re-used in a
|
||||
GPL bootloader, and as the author of that code, I would be happy
|
||||
to discuss possible free licensing to any vendor who wishes to
|
||||
integrate all or part of this code into a non-GPL bootloader.
|
||||
(reference needed; who is 'I' here? ---gcl Jan 31, 2011)
|
||||
|
||||
|
||||
|
||||
@ -1203,18 +1145,19 @@ MPC8540.
|
||||
2) Representing devices without a current OF specification
|
||||
----------------------------------------------------------
|
||||
|
||||
Currently, there are many devices on SOCs that do not have a standard
|
||||
representation pre-defined as part of the open firmware
|
||||
specifications, mainly because the boards that contain these SOCs are
|
||||
not currently booted using open firmware. This section contains
|
||||
descriptions for the SOC devices for which new nodes have been
|
||||
defined; this list will expand as more and more SOC-containing
|
||||
platforms are moved over to use the flattened-device-tree model.
|
||||
Currently, there are many devices on SoCs that do not have a standard
|
||||
representation defined as part of the Open Firmware specifications,
|
||||
mainly because the boards that contain these SoCs are not currently
|
||||
booted using Open Firmware. Binding documentation for new devices
|
||||
should be added to the Documentation/devicetree/bindings directory.
|
||||
That directory will expand as device tree support is added to more and
|
||||
more SoCs.
|
||||
|
||||
|
||||
VII - Specifying interrupt information for devices
|
||||
===================================================
|
||||
|
||||
The device tree represents the busses and devices of a hardware
|
||||
The device tree represents the buses and devices of a hardware
|
||||
system in a form similar to the physical bus topology of the
|
||||
hardware.
|
||||
|
@ -51,7 +51,8 @@ Supported chips:
|
||||
* JEDEC JC 42.4 compliant temperature sensor chips
|
||||
Prefix: 'jc42'
|
||||
Addresses scanned: I2C 0x18 - 0x1f
|
||||
Datasheet: -
|
||||
Datasheet:
|
||||
http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
|
||||
|
||||
Author:
|
||||
Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
@ -60,7 +61,11 @@ Author:
|
||||
Description
|
||||
-----------
|
||||
|
||||
This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
|
||||
This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
|
||||
which are used on many DDR3 memory modules for mobile devices and servers. Some
|
||||
systems use the sensor to prevent memory overheating by automatically throttling
|
||||
the memory controller.
|
||||
|
||||
The driver auto-detects the chips listed above, but can be manually instantiated
|
||||
to support other JC 42.4 compliant chips.
|
||||
|
||||
@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
|
||||
which applies to all limits. This register can be written by writing into
|
||||
temp1_crit_hyst. Other hysteresis attributes are read-only.
|
||||
|
||||
If the BIOS has configured the sensor for automatic temperature management, it
|
||||
is likely that it has locked the registers, i.e., that the temperature limits
|
||||
cannot be changed.
|
||||
|
||||
Sysfs entries
|
||||
-------------
|
||||
|
||||
temp1_input Temperature (RO)
|
||||
temp1_min Minimum temperature (RW)
|
||||
temp1_max Maximum temperature (RW)
|
||||
temp1_crit Critical high temperature (RW)
|
||||
temp1_min Minimum temperature (RO or RW)
|
||||
temp1_max Maximum temperature (RO or RW)
|
||||
temp1_crit Critical high temperature (RO or RW)
|
||||
|
||||
temp1_crit_hyst Critical hysteresis temperature (RW)
|
||||
temp1_crit_hyst Critical hysteresis temperature (RO or RW)
|
||||
temp1_max_hyst Maximum hysteresis temperature (RO)
|
||||
|
||||
temp1_min_alarm Temperature low alarm
|
||||
|
@ -9,6 +9,8 @@ Supported chips:
|
||||
Socket S1G3: Athlon II, Sempron, Turion II
|
||||
* AMD Family 11h processors:
|
||||
Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
|
||||
* AMD Family 12h processors: "Llano"
|
||||
* AMD Family 14h processors: "Brazos" (C/E/G-Series)
|
||||
|
||||
Prefix: 'k10temp'
|
||||
Addresses scanned: PCI space
|
||||
@ -17,10 +19,14 @@ Supported chips:
|
||||
http://support.amd.com/us/Processor_TechDocs/31116.pdf
|
||||
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
|
||||
http://support.amd.com/us/Processor_TechDocs/41256.pdf
|
||||
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
|
||||
http://support.amd.com/us/Processor_TechDocs/43170.pdf
|
||||
Revision Guide for AMD Family 10h Processors:
|
||||
http://support.amd.com/us/Processor_TechDocs/41322.pdf
|
||||
Revision Guide for AMD Family 11h Processors:
|
||||
http://support.amd.com/us/Processor_TechDocs/41788.pdf
|
||||
Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
|
||||
http://support.amd.com/us/Processor_TechDocs/47534.pdf
|
||||
AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
|
||||
http://support.amd.com/us/Processor_TechDocs/43373.pdf
|
||||
AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
|
||||
@ -34,7 +40,7 @@ Description
|
||||
-----------
|
||||
|
||||
This driver permits reading of the internal temperature sensor of AMD
|
||||
Family 10h and 11h processors.
|
||||
Family 10h/11h/12h/14h processors.
|
||||
|
||||
All these processors have a sensor, but on those for Socket F or AM2+,
|
||||
the sensor may return inconsistent values (erratum 319). The driver
|
||||
|
@ -144,6 +144,11 @@ a fixed number of characters. This limit depends on the architecture
|
||||
and is between 256 and 4096 characters. It is defined in the file
|
||||
./include/asm/setup.h as COMMAND_LINE_SIZE.
|
||||
|
||||
Finally, the [KMG] suffix is commonly described after a number of kernel
|
||||
parameter values. These 'K', 'M', and 'G' letters represent the _binary_
|
||||
multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
|
||||
bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
|
||||
|
||||
acpi= [HW,ACPI,X86]
|
||||
Advanced Configuration and Power Interface
|
||||
@ -545,16 +550,20 @@ and is between 256 and 4096 characters. It is defined in the file
|
||||
Format:
|
||||
<first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
|
||||
|
||||
crashkernel=nn[KMG]@ss[KMG]
|
||||
[KNL] Reserve a chunk of physical memory to
|
||||
hold a kernel to switch to with kexec on panic.
|
||||
crashkernel=size[KMG][@offset[KMG]]
|
||||
[KNL] Using kexec, Linux can switch to a 'crash kernel'
|
||||
upon panic. This parameter reserves the physical
|
||||
memory region [offset, offset + size] for that kernel
|
||||
image. If '@offset' is omitted, then a suitable offset
|
||||
is selected automatically. Check
|
||||
Documentation/kdump/kdump.txt for further details.
|
||||
|
||||
crashkernel=range1:size1[,range2:size2,...][@offset]
|
||||
[KNL] Same as above, but depends on the memory
|
||||
in the running system. The syntax of range is
|
||||
start-[end] where start and end are both
|
||||
a memory unit (amount[KMG]). See also
|
||||
Documentation/kdump/kdump.txt for a example.
|
||||
Documentation/kdump/kdump.txt for an example.
|
||||
|
||||
cs89x0_dma= [HW,NET]
|
||||
Format: <dma>
|
||||
@ -1262,10 +1271,9 @@ and is between 256 and 4096 characters. It is defined in the file
|
||||
6 (KERN_INFO) informational
|
||||
7 (KERN_DEBUG) debug-level messages
|
||||
|
||||
log_buf_len=n Sets the size of the printk ring buffer, in bytes.
|
||||
Format: { n | nk | nM }
|
||||
n must be a power of two. The default size
|
||||
is set in the kernel config file.
|
||||
log_buf_len=n[KMG] Sets the size of the printk ring buffer,
|
||||
in bytes. n must be a power of two. The default
|
||||
size is set in the kernel config file.
|
||||
|
||||
logo.nologo [FB] Disables display of the built-in Linux logo.
|
||||
This may be used to provide more screen space for
|
||||
|
@ -40,8 +40,6 @@ decnet.txt
|
||||
- info on using the DECnet networking layer in Linux.
|
||||
depca.txt
|
||||
- the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
|
||||
dgrs.txt
|
||||
- the Digi International RightSwitch SE-X Ethernet driver
|
||||
dmfe.txt
|
||||
- info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
|
||||
e100.txt
|
||||
@ -50,8 +48,6 @@ e1000.txt
|
||||
- info on Intel's E1000 line of gigabit ethernet boards
|
||||
eql.txt
|
||||
- serial IP load balancing
|
||||
ethertap.txt
|
||||
- the Ethertap user space packet reception and transmission driver
|
||||
ewrk3.txt
|
||||
- the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
|
||||
filter.txt
|
||||
@ -104,8 +100,6 @@ tuntap.txt
|
||||
- TUN/TAP device driver, allowing user space Rx/Tx of packets.
|
||||
vortex.txt
|
||||
- info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
|
||||
wavelan.txt
|
||||
- AT&T GIS (nee NCR) WaveLAN card: An Ethernet-like radio transceiver
|
||||
x25.txt
|
||||
- general info on X.25 development.
|
||||
x25-iface.txt
|
||||
|
@ -4,6 +4,8 @@ obj- := dummy.o
|
||||
# List of programs to build
|
||||
hostprogs-y := ifenslave
|
||||
|
||||
HOSTCFLAGS_ifenslave.o += -I$(objtree)/usr/include
|
||||
|
||||
# Tell kbuild to always build the programs
|
||||
always := $(hostprogs-y)
|
||||
|
||||
|
@ -61,7 +61,6 @@ before the more general line given above as the first match is the one taken.
|
||||
create dns_resolver foo:* * /usr/sbin/dns.foo %k
|
||||
|
||||
|
||||
|
||||
=====
|
||||
USAGE
|
||||
=====
|
||||
@ -104,6 +103,14 @@ implemented in the module can be called after doing:
|
||||
returned also.
|
||||
|
||||
|
||||
===============================
|
||||
READING DNS KEYS FROM USERSPACE
|
||||
===============================
|
||||
|
||||
Keys of dns_resolver type can be read from userspace using keyctl_read() or
|
||||
"keyctl read/print/pipe".
|
||||
|
||||
|
||||
=========
|
||||
MECHANISM
|
||||
=========
|
||||
|
@ -190,9 +190,9 @@ resources, scheduled and executed.
|
||||
* Long running CPU intensive workloads which can be better
|
||||
managed by the system scheduler.
|
||||
|
||||
WQ_FREEZEABLE
|
||||
WQ_FREEZABLE
|
||||
|
||||
A freezeable wq participates in the freeze phase of the system
|
||||
A freezable wq participates in the freeze phase of the system
|
||||
suspend operations. Work items on the wq are drained and no
|
||||
new work item starts execution until thawed.
|
||||
|
||||
|
41
MAINTAINERS
41
MAINTAINERS
@ -885,7 +885,7 @@ S: Supported
|
||||
|
||||
ARM/QUALCOMM MSM MACHINE SUPPORT
|
||||
M: David Brown <davidb@codeaurora.org>
|
||||
M: Daniel Walker <dwalker@codeaurora.org>
|
||||
M: Daniel Walker <dwalker@fifo99.com>
|
||||
M: Bryan Huntsman <bryanh@codeaurora.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
F: arch/arm/mach-msm/
|
||||
@ -1010,6 +1010,15 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-s5p*/
|
||||
|
||||
ARM/SAMSUNG MOBILE MACHINE SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-s5pv210/mach-aquila.c
|
||||
F: arch/arm/mach-s5pv210/mach-goni.c
|
||||
F: arch/arm/mach-exynos4/mach-universal_c210.c
|
||||
F: arch/arm/mach-exynos4/mach-nuri.c
|
||||
|
||||
ARM/SAMSUNG S5P SERIES FIMC SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
@ -1467,6 +1476,7 @@ F: include/net/bluetooth/
|
||||
|
||||
BONDING DRIVER
|
||||
M: Jay Vosburgh <fubar@us.ibm.com>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/bonding/
|
||||
S: Supported
|
||||
@ -1692,6 +1702,13 @@ M: Andy Whitcroft <apw@canonical.com>
|
||||
S: Supported
|
||||
F: scripts/checkpatch.pl
|
||||
|
||||
CHINESE DOCUMENTATION
|
||||
M: Harry Wei <harryxiyou@gmail.com>
|
||||
L: xiyoulinuxkernelgroup@googlegroups.com
|
||||
L: linux-kernel@zh-kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/zh_CN/
|
||||
|
||||
CISCO VIC ETHERNET NIC DRIVER
|
||||
M: Vasanthy Kolluri <vkolluri@cisco.com>
|
||||
M: Roopa Prabhu <roprabhu@cisco.com>
|
||||
@ -2026,7 +2043,7 @@ F: Documentation/scsi/dc395x.txt
|
||||
F: drivers/scsi/dc395x.*
|
||||
|
||||
DCCP PROTOCOL
|
||||
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
|
||||
M: Gerrit Renker <gerrit@erg.abdn.ac.uk>
|
||||
L: dccp@vger.kernel.org
|
||||
W: http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
|
||||
S: Maintained
|
||||
@ -2126,6 +2143,7 @@ S: Supported
|
||||
F: fs/dlm/
|
||||
|
||||
DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
|
||||
M: Vinod Koul <vinod.koul@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
S: Supported
|
||||
F: drivers/dma/
|
||||
@ -2774,6 +2792,15 @@ F: Documentation/isdn/README.gigaset
|
||||
F: drivers/isdn/gigaset/
|
||||
F: include/linux/gigaset_dev.h
|
||||
|
||||
GPIO SUBSYSTEM
|
||||
M: Grant Likely <grant.likely@secretlab.ca>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.secretlab.ca/git/linux-2.6.git
|
||||
F: Documentation/gpio/gpio.txt
|
||||
F: drivers/gpio/
|
||||
F: include/linux/gpio*
|
||||
|
||||
GRETH 10/100/1G Ethernet MAC device driver
|
||||
M: Kristoffer Glembo <kristoffer@gaisler.com>
|
||||
L: netdev@vger.kernel.org
|
||||
@ -2863,7 +2890,6 @@ M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/
|
||||
@ -3503,7 +3529,7 @@ F: drivers/hwmon/jc42.c
|
||||
F: Documentation/hwmon/jc42
|
||||
|
||||
JFS FILESYSTEM
|
||||
M: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
|
||||
M: Dave Kleikamp <shaggy@kernel.org>
|
||||
L: jfs-discussion@lists.sourceforge.net
|
||||
W: http://jfs.sourceforge.net/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6.git
|
||||
@ -4591,7 +4617,7 @@ F: drivers/i2c/busses/i2c-ocores.c
|
||||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Grant Likely <grant.likely@secretlab.ca>
|
||||
L: devicetree-discuss@lists.ozlabs.org
|
||||
L: devicetree-discuss@lists.ozlabs.org (moderated for non-subscribers)
|
||||
W: http://fdt.secretlab.ca
|
||||
T: git git://git.secretlab.ca/git/linux-2.6.git
|
||||
S: Maintained
|
||||
@ -5155,6 +5181,7 @@ F: drivers/char/random.c
|
||||
|
||||
RAPIDIO SUBSYSTEM
|
||||
M: Matt Porter <mporter@kernel.crashing.org>
|
||||
M: Alexandre Bounine <alexandre.bounine@idt.com>
|
||||
S: Maintained
|
||||
F: drivers/rapidio/
|
||||
|
||||
@ -5257,7 +5284,7 @@ S: Maintained
|
||||
F: drivers/net/wireless/rtl818x/rtl8180/
|
||||
|
||||
RTL8187 WIRELESS DRIVER
|
||||
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
|
||||
M: Herton Ronaldo Krzesinski <herton@canonical.com>
|
||||
M: Hin-Tak Leung <htl10@users.sourceforge.net>
|
||||
M: Larry Finger <Larry.Finger@lwfinger.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
@ -6095,7 +6122,7 @@ S: Maintained
|
||||
F: security/tomoyo/
|
||||
|
||||
TOPSTAR LAPTOP EXTRAS DRIVER
|
||||
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
|
||||
M: Herton Ronaldo Krzesinski <herton@canonical.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/topstar-laptop.c
|
||||
|
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 38
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = Flesh-Eating Bats with Fangs
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -11,6 +11,7 @@ config ALPHA
|
||||
select HAVE_GENERIC_HARDIRQS
|
||||
select GENERIC_IRQ_PROBE
|
||||
select AUTO_IRQ_AFFINITY if SMP
|
||||
select GENERIC_HARDIRQS_NO_DEPRECATED
|
||||
help
|
||||
The Alpha is a 64-bit general-purpose processor designed and
|
||||
marketed by the Digital Equipment Corporation of blessed memory,
|
||||
|
@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
|
||||
|
||||
int irq_select_affinity(unsigned int irq)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc[irq];
|
||||
struct irq_data *data = irq_get_irq_data(irq);
|
||||
struct irq_chip *chip;
|
||||
static int last_cpu;
|
||||
int cpu = last_cpu + 1;
|
||||
|
||||
if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
|
||||
if (!data)
|
||||
return 1;
|
||||
chip = irq_data_get_irq_chip(data);
|
||||
|
||||
if (!chip->irq_set_affinity || irq_user_affinity[irq])
|
||||
return 1;
|
||||
|
||||
while (!cpu_possible(cpu) ||
|
||||
@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
|
||||
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
|
||||
last_cpu = cpu;
|
||||
|
||||
cpumask_copy(desc->affinity, cpumask_of(cpu));
|
||||
get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
|
||||
cpumask_copy(data->affinity, cpumask_of(cpu));
|
||||
chip->irq_set_affinity(data, cpumask_of(cpu), false);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
|
||||
void __init
|
||||
init_rtc_irq(void)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(RTC_IRQ);
|
||||
|
||||
if (desc) {
|
||||
desc->status |= IRQ_DISABLED;
|
||||
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
handle_simple_irq, "RTC");
|
||||
setup_irq(RTC_IRQ, &timer_irqaction);
|
||||
}
|
||||
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
|
||||
handle_simple_irq, "RTC");
|
||||
setup_irq(RTC_IRQ, &timer_irqaction);
|
||||
}
|
||||
|
||||
/* Dummy irqactions. */
|
||||
|
@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
|
||||
}
|
||||
|
||||
inline void
|
||||
i8259a_enable_irq(unsigned int irq)
|
||||
i8259a_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&i8259_irq_lock);
|
||||
i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
|
||||
i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
|
||||
spin_unlock(&i8259_irq_lock);
|
||||
}
|
||||
|
||||
@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
void
|
||||
i8259a_disable_irq(unsigned int irq)
|
||||
i8259a_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&i8259_irq_lock);
|
||||
__i8259a_disable_irq(irq);
|
||||
__i8259a_disable_irq(d->irq);
|
||||
spin_unlock(&i8259_irq_lock);
|
||||
}
|
||||
|
||||
void
|
||||
i8259a_mask_and_ack_irq(unsigned int irq)
|
||||
i8259a_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
spin_lock(&i8259_irq_lock);
|
||||
__i8259a_disable_irq(irq);
|
||||
|
||||
@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
struct irq_chip i8259a_irq_type = {
|
||||
.name = "XT-PIC",
|
||||
.unmask = i8259a_enable_irq,
|
||||
.mask = i8259a_disable_irq,
|
||||
.mask_ack = i8259a_mask_and_ack_irq,
|
||||
.irq_unmask = i8259a_enable_irq,
|
||||
.irq_mask = i8259a_disable_irq,
|
||||
.irq_mask_ack = i8259a_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
void __init
|
||||
|
@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
|
||||
|
||||
extern void common_init_isa_dma(void);
|
||||
|
||||
extern void i8259a_enable_irq(unsigned int);
|
||||
extern void i8259a_disable_irq(unsigned int);
|
||||
extern void i8259a_mask_and_ack_irq(unsigned int);
|
||||
extern unsigned int i8259a_startup_irq(unsigned int);
|
||||
extern void i8259a_end_irq(unsigned int);
|
||||
extern void i8259a_enable_irq(struct irq_data *d);
|
||||
extern void i8259a_disable_irq(struct irq_data *d);
|
||||
extern void i8259a_mask_and_ack_irq(struct irq_data *d);
|
||||
extern struct irq_chip i8259a_irq_type;
|
||||
extern void init_i8259a_irqs(void);
|
||||
|
||||
|
@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
pyxis_enable_irq(unsigned int irq)
|
||||
pyxis_enable_irq(struct irq_data *d)
|
||||
{
|
||||
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
pyxis_disable_irq(unsigned int irq)
|
||||
pyxis_disable_irq(struct irq_data *d)
|
||||
{
|
||||
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static void
|
||||
pyxis_mask_and_ack_irq(unsigned int irq)
|
||||
pyxis_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit = 1UL << (irq - 16);
|
||||
unsigned long bit = 1UL << (d->irq - 16);
|
||||
unsigned long mask = cached_irq_mask &= ~bit;
|
||||
|
||||
/* Disable the interrupt. */
|
||||
@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip pyxis_irq_type = {
|
||||
.name = "PYXIS",
|
||||
.mask_ack = pyxis_mask_and_ack_irq,
|
||||
.mask = pyxis_disable_irq,
|
||||
.unmask = pyxis_enable_irq,
|
||||
.irq_mask_ack = pyxis_mask_and_ack_irq,
|
||||
.irq_mask = pyxis_disable_irq,
|
||||
.irq_unmask = pyxis_enable_irq,
|
||||
};
|
||||
|
||||
void
|
||||
@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
|
||||
if ((ignore_mask >> i) & 1)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
setup_irq(16+7, &isa_cascade_irqaction);
|
||||
|
@ -18,27 +18,27 @@
|
||||
DEFINE_SPINLOCK(srm_irq_lock);
|
||||
|
||||
static inline void
|
||||
srm_enable_irq(unsigned int irq)
|
||||
srm_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&srm_irq_lock);
|
||||
cserve_ena(irq - 16);
|
||||
cserve_ena(d->irq - 16);
|
||||
spin_unlock(&srm_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
srm_disable_irq(unsigned int irq)
|
||||
srm_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&srm_irq_lock);
|
||||
cserve_dis(irq - 16);
|
||||
cserve_dis(d->irq - 16);
|
||||
spin_unlock(&srm_irq_lock);
|
||||
}
|
||||
|
||||
/* Handle interrupts from the SRM, assuming no additional weirdness. */
|
||||
static struct irq_chip srm_irq_type = {
|
||||
.name = "SRM",
|
||||
.unmask = srm_enable_irq,
|
||||
.mask = srm_disable_irq,
|
||||
.mask_ack = srm_disable_irq,
|
||||
.irq_unmask = srm_enable_irq,
|
||||
.irq_mask = srm_disable_irq,
|
||||
.irq_mask_ack = srm_disable_irq,
|
||||
};
|
||||
|
||||
void __init
|
||||
@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
|
||||
if (i < 64 && ((ignore_mask >> i) & 1))
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
alcor_enable_irq(unsigned int irq)
|
||||
alcor_enable_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_disable_irq(unsigned int irq)
|
||||
alcor_disable_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_mask_and_ack_irq(unsigned int irq)
|
||||
alcor_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
alcor_disable_irq(irq);
|
||||
alcor_disable_irq(d);
|
||||
|
||||
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
|
||||
*(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
|
||||
*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
|
||||
*(vuip)GRU_INT_CLEAR = 0; mb();
|
||||
}
|
||||
|
||||
static void
|
||||
alcor_isa_mask_and_ack_irq(unsigned int irq)
|
||||
alcor_isa_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
i8259a_mask_and_ack_irq(irq);
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
|
||||
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
|
||||
*(vuip)GRU_INT_CLEAR = 0x80000000; mb();
|
||||
@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip alcor_irq_type = {
|
||||
.name = "ALCOR",
|
||||
.unmask = alcor_enable_irq,
|
||||
.mask = alcor_disable_irq,
|
||||
.mask_ack = alcor_mask_and_ack_irq,
|
||||
.irq_unmask = alcor_enable_irq,
|
||||
.irq_mask = alcor_disable_irq,
|
||||
.irq_mask_ack = alcor_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -126,9 +126,9 @@ alcor_init_irq(void)
|
||||
if (i >= 16+20 && i <= 16+30)
|
||||
continue;
|
||||
set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
|
||||
i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
|
||||
|
||||
init_i8259a_irqs();
|
||||
common_init_isa_dma();
|
||||
|
@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
cabriolet_enable_irq(unsigned int irq)
|
||||
cabriolet_enable_irq(struct irq_data *d)
|
||||
{
|
||||
cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
|
||||
cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
|
||||
}
|
||||
|
||||
static void
|
||||
cabriolet_disable_irq(unsigned int irq)
|
||||
cabriolet_disable_irq(struct irq_data *d)
|
||||
{
|
||||
cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
|
||||
cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
|
||||
}
|
||||
|
||||
static struct irq_chip cabriolet_irq_type = {
|
||||
.name = "CABRIOLET",
|
||||
.unmask = cabriolet_enable_irq,
|
||||
.mask = cabriolet_disable_irq,
|
||||
.mask_ack = cabriolet_disable_irq,
|
||||
.irq_unmask = cabriolet_enable_irq,
|
||||
.irq_mask = cabriolet_disable_irq,
|
||||
.irq_mask_ack = cabriolet_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
|
||||
for (i = 16; i < 35; ++i) {
|
||||
set_irq_chip_and_handler(i, &cabriolet_irq_type,
|
||||
handle_level_irq);
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
|
||||
}
|
||||
|
||||
static void
|
||||
dp264_enable_irq(unsigned int irq)
|
||||
dp264_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask |= 1UL << irq;
|
||||
cached_irq_mask |= 1UL << d->irq;
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
dp264_disable_irq(unsigned int irq)
|
||||
dp264_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask &= ~(1UL << irq);
|
||||
cached_irq_mask &= ~(1UL << d->irq);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
clipper_enable_irq(unsigned int irq)
|
||||
clipper_enable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask |= 1UL << (irq - 16);
|
||||
cached_irq_mask |= 1UL << (d->irq - 16);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
|
||||
static void
|
||||
clipper_disable_irq(unsigned int irq)
|
||||
clipper_disable_irq(struct irq_data *d)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cached_irq_mask &= ~(1UL << (irq - 16));
|
||||
cached_irq_mask &= ~(1UL << (d->irq - 16));
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
}
|
||||
@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
||||
}
|
||||
|
||||
static int
|
||||
dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
{
|
||||
dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cpu_set_irq_affinity(irq, *affinity);
|
||||
cpu_set_irq_affinity(d->irq, *affinity);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
|
||||
@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
}
|
||||
|
||||
static int
|
||||
clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
{
|
||||
clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&dp264_irq_lock);
|
||||
cpu_set_irq_affinity(irq - 16, *affinity);
|
||||
cpu_set_irq_affinity(d->irq - 16, *affinity);
|
||||
tsunami_update_irq_hw(cached_irq_mask);
|
||||
spin_unlock(&dp264_irq_lock);
|
||||
|
||||
@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
}
|
||||
|
||||
static struct irq_chip dp264_irq_type = {
|
||||
.name = "DP264",
|
||||
.unmask = dp264_enable_irq,
|
||||
.mask = dp264_disable_irq,
|
||||
.mask_ack = dp264_disable_irq,
|
||||
.set_affinity = dp264_set_affinity,
|
||||
.name = "DP264",
|
||||
.irq_unmask = dp264_enable_irq,
|
||||
.irq_mask = dp264_disable_irq,
|
||||
.irq_mask_ack = dp264_disable_irq,
|
||||
.irq_set_affinity = dp264_set_affinity,
|
||||
};
|
||||
|
||||
static struct irq_chip clipper_irq_type = {
|
||||
.name = "CLIPPER",
|
||||
.unmask = clipper_enable_irq,
|
||||
.mask = clipper_disable_irq,
|
||||
.mask_ack = clipper_disable_irq,
|
||||
.set_affinity = clipper_set_affinity,
|
||||
.name = "CLIPPER",
|
||||
.irq_unmask = clipper_enable_irq,
|
||||
.irq_mask = clipper_disable_irq,
|
||||
.irq_mask_ack = clipper_disable_irq,
|
||||
.irq_set_affinity = clipper_set_affinity,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
|
||||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
eb64p_enable_irq(unsigned int irq)
|
||||
eb64p_enable_irq(struct irq_data *d)
|
||||
{
|
||||
eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
|
||||
eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
|
||||
}
|
||||
|
||||
static void
|
||||
eb64p_disable_irq(unsigned int irq)
|
||||
eb64p_disable_irq(struct irq_data *d)
|
||||
{
|
||||
eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
|
||||
eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
|
||||
}
|
||||
|
||||
static struct irq_chip eb64p_irq_type = {
|
||||
.name = "EB64P",
|
||||
.unmask = eb64p_enable_irq,
|
||||
.mask = eb64p_disable_irq,
|
||||
.mask_ack = eb64p_disable_irq,
|
||||
.irq_unmask = eb64p_enable_irq,
|
||||
.irq_mask = eb64p_disable_irq,
|
||||
.irq_mask_ack = eb64p_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -118,9 +118,9 @@ eb64p_init_irq(void)
|
||||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
|
||||
}
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
setup_irq(16+5, &isa_cascade_irqaction);
|
||||
|
@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
eiger_enable_irq(unsigned int irq)
|
||||
eiger_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
|
||||
eiger_update_irq_hw(irq, mask);
|
||||
}
|
||||
|
||||
static void
|
||||
eiger_disable_irq(unsigned int irq)
|
||||
eiger_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
|
||||
eiger_update_irq_hw(irq, mask);
|
||||
@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip eiger_irq_type = {
|
||||
.name = "EIGER",
|
||||
.unmask = eiger_enable_irq,
|
||||
.mask = eiger_disable_irq,
|
||||
.mask_ack = eiger_disable_irq,
|
||||
.irq_unmask = eiger_enable_irq,
|
||||
.irq_mask = eiger_disable_irq,
|
||||
.irq_mask_ack = eiger_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -136,8 +138,8 @@ eiger_init_irq(void)
|
||||
init_i8259a_irqs();
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -63,34 +63,34 @@
|
||||
*/
|
||||
|
||||
static void
|
||||
jensen_local_enable(unsigned int irq)
|
||||
jensen_local_enable(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_enable_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_enable_irq(d);
|
||||
}
|
||||
|
||||
static void
|
||||
jensen_local_disable(unsigned int irq)
|
||||
jensen_local_disable(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_disable_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_disable_irq(d);
|
||||
}
|
||||
|
||||
static void
|
||||
jensen_local_mask_ack(unsigned int irq)
|
||||
jensen_local_mask_ack(struct irq_data *d)
|
||||
{
|
||||
/* the parport is really hw IRQ 1, silly Jensen. */
|
||||
if (irq == 7)
|
||||
i8259a_mask_and_ack_irq(1);
|
||||
if (d->irq == 7)
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
}
|
||||
|
||||
static struct irq_chip jensen_local_irq_type = {
|
||||
.name = "LOCAL",
|
||||
.unmask = jensen_local_enable,
|
||||
.mask = jensen_local_disable,
|
||||
.mask_ack = jensen_local_mask_ack,
|
||||
.irq_unmask = jensen_local_enable,
|
||||
.irq_mask = jensen_local_disable,
|
||||
.irq_mask_ack = jensen_local_mask_ack,
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
|
||||
}
|
||||
|
||||
static void
|
||||
io7_enable_irq(unsigned int irq)
|
||||
io7_enable_irq(struct irq_data *d)
|
||||
{
|
||||
volatile unsigned long *ctl;
|
||||
unsigned int irq = d->irq;
|
||||
struct io7 *io7;
|
||||
|
||||
ctl = io7_get_irq_ctl(irq, &io7);
|
||||
@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
|
||||
__func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
spin_lock(&io7->irq_lock);
|
||||
*ctl |= 1UL << 24;
|
||||
mb();
|
||||
@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
io7_disable_irq(unsigned int irq)
|
||||
io7_disable_irq(struct irq_data *d)
|
||||
{
|
||||
volatile unsigned long *ctl;
|
||||
unsigned int irq = d->irq;
|
||||
struct io7 *io7;
|
||||
|
||||
ctl = io7_get_irq_ctl(irq, &io7);
|
||||
@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
|
||||
__func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
spin_lock(&io7->irq_lock);
|
||||
*ctl &= ~(1UL << 24);
|
||||
mb();
|
||||
@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
marvel_irq_noop(unsigned int irq)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
marvel_irq_noop_return(unsigned int irq)
|
||||
{
|
||||
return 0;
|
||||
marvel_irq_noop(struct irq_data *d)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static struct irq_chip marvel_legacy_irq_type = {
|
||||
.name = "LEGACY",
|
||||
.mask = marvel_irq_noop,
|
||||
.unmask = marvel_irq_noop,
|
||||
.irq_mask = marvel_irq_noop,
|
||||
.irq_unmask = marvel_irq_noop,
|
||||
};
|
||||
|
||||
static struct irq_chip io7_lsi_irq_type = {
|
||||
.name = "LSI",
|
||||
.unmask = io7_enable_irq,
|
||||
.mask = io7_disable_irq,
|
||||
.mask_ack = io7_disable_irq,
|
||||
.irq_unmask = io7_enable_irq,
|
||||
.irq_mask = io7_disable_irq,
|
||||
.irq_mask_ack = io7_disable_irq,
|
||||
};
|
||||
|
||||
static struct irq_chip io7_msi_irq_type = {
|
||||
.name = "MSI",
|
||||
.unmask = io7_enable_irq,
|
||||
.mask = io7_disable_irq,
|
||||
.ack = marvel_irq_noop,
|
||||
.irq_unmask = io7_enable_irq,
|
||||
.irq_mask = io7_disable_irq,
|
||||
.irq_ack = marvel_irq_noop,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
|
||||
|
||||
/* Set up the lsi irqs. */
|
||||
for (i = 0; i < 128; ++i) {
|
||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
/* Disable the implemented irqs in hardware. */
|
||||
@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
|
||||
|
||||
/* Set up the msi irqs. */
|
||||
for (i = 128; i < (128 + 512); ++i) {
|
||||
irq_to_desc(base + i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; ++i)
|
||||
|
@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
mikasa_enable_irq(unsigned int irq)
|
||||
mikasa_enable_irq(struct irq_data *d)
|
||||
{
|
||||
mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
|
||||
mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
mikasa_disable_irq(unsigned int irq)
|
||||
mikasa_disable_irq(struct irq_data *d)
|
||||
{
|
||||
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
|
||||
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip mikasa_irq_type = {
|
||||
.name = "MIKASA",
|
||||
.unmask = mikasa_enable_irq,
|
||||
.mask = mikasa_disable_irq,
|
||||
.mask_ack = mikasa_disable_irq,
|
||||
.irq_unmask = mikasa_enable_irq,
|
||||
.irq_mask = mikasa_disable_irq,
|
||||
.irq_mask_ack = mikasa_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -98,8 +98,8 @@ mikasa_init_irq(void)
|
||||
mikasa_update_irq_hw(0);
|
||||
|
||||
for (i = 16; i < 32; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
|
||||
}
|
||||
|
||||
static void
|
||||
noritake_enable_irq(unsigned int irq)
|
||||
noritake_enable_irq(struct irq_data *d)
|
||||
{
|
||||
noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
|
||||
noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
noritake_disable_irq(unsigned int irq)
|
||||
noritake_disable_irq(struct irq_data *d)
|
||||
{
|
||||
noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
|
||||
noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip noritake_irq_type = {
|
||||
.name = "NORITAKE",
|
||||
.unmask = noritake_enable_irq,
|
||||
.mask = noritake_disable_irq,
|
||||
.mask_ack = noritake_disable_irq,
|
||||
.irq_unmask = noritake_enable_irq,
|
||||
.irq_mask = noritake_disable_irq,
|
||||
.irq_mask_ack = noritake_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -127,8 +127,8 @@ noritake_init_irq(void)
|
||||
outw(0, 0x54c);
|
||||
|
||||
for (i = 16; i < 48; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
|
||||
(((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
|
||||
|
||||
static inline void
|
||||
rawhide_enable_irq(unsigned int irq)
|
||||
rawhide_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
rawhide_disable_irq(unsigned int irq)
|
||||
rawhide_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
rawhide_mask_and_ack_irq(unsigned int irq)
|
||||
rawhide_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int mask, mask1, hose;
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
irq -= 16;
|
||||
hose = irq / 24;
|
||||
@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip rawhide_irq_type = {
|
||||
.name = "RAWHIDE",
|
||||
.unmask = rawhide_enable_irq,
|
||||
.mask = rawhide_disable_irq,
|
||||
.mask_ack = rawhide_mask_and_ack_irq,
|
||||
.irq_unmask = rawhide_enable_irq,
|
||||
.irq_mask = rawhide_disable_irq,
|
||||
.irq_mask_ack = rawhide_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -177,8 +180,8 @@ rawhide_init_irq(void)
|
||||
}
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
rx164_enable_irq(unsigned int irq)
|
||||
rx164_enable_irq(struct irq_data *d)
|
||||
{
|
||||
rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
|
||||
rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
|
||||
}
|
||||
|
||||
static void
|
||||
rx164_disable_irq(unsigned int irq)
|
||||
rx164_disable_irq(struct irq_data *d)
|
||||
{
|
||||
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
|
||||
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
|
||||
}
|
||||
|
||||
static struct irq_chip rx164_irq_type = {
|
||||
.name = "RX164",
|
||||
.unmask = rx164_enable_irq,
|
||||
.mask = rx164_disable_irq,
|
||||
.mask_ack = rx164_disable_irq,
|
||||
.irq_unmask = rx164_enable_irq,
|
||||
.irq_mask = rx164_disable_irq,
|
||||
.irq_mask_ack = rx164_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -99,8 +99,8 @@ rx164_init_irq(void)
|
||||
|
||||
rx164_update_irq_hw(0);
|
||||
for (i = 16; i < 40; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
init_i8259a_irqs();
|
||||
|
@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
/* GENERIC irq routines */
|
||||
|
||||
static inline void
|
||||
sable_lynx_enable_irq(unsigned int irq)
|
||||
sable_lynx_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
sable_lynx_disable_irq(unsigned int irq)
|
||||
sable_lynx_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
sable_lynx_mask_and_ack_irq(unsigned int irq)
|
||||
sable_lynx_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long bit, mask;
|
||||
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
|
||||
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
|
||||
spin_lock(&sable_lynx_irq_lock);
|
||||
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
|
||||
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
|
||||
@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip sable_lynx_irq_type = {
|
||||
.name = "SABLE/LYNX",
|
||||
.unmask = sable_lynx_enable_irq,
|
||||
.mask = sable_lynx_disable_irq,
|
||||
.mask_ack = sable_lynx_mask_and_ack_irq,
|
||||
.irq_unmask = sable_lynx_enable_irq,
|
||||
.irq_mask = sable_lynx_disable_irq,
|
||||
.irq_mask_ack = sable_lynx_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
|
||||
long i;
|
||||
|
||||
for (i = 0; i < nr_of_irqs; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
|
@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
takara_enable_irq(unsigned int irq)
|
||||
takara_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
|
||||
takara_update_irq_hw(irq, mask);
|
||||
}
|
||||
|
||||
static void
|
||||
takara_disable_irq(unsigned int irq)
|
||||
takara_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
unsigned long mask;
|
||||
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
|
||||
takara_update_irq_hw(irq, mask);
|
||||
@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip takara_irq_type = {
|
||||
.name = "TAKARA",
|
||||
.unmask = takara_enable_irq,
|
||||
.mask = takara_disable_irq,
|
||||
.mask_ack = takara_disable_irq,
|
||||
.irq_unmask = takara_enable_irq,
|
||||
.irq_mask = takara_disable_irq,
|
||||
.irq_mask_ack = takara_disable_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
@ -136,8 +138,8 @@ takara_init_irq(void)
|
||||
takara_update_irq_hw(i, -1);
|
||||
|
||||
for (i = 16; i < 128; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
common_init_isa_dma();
|
||||
|
@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
|
||||
}
|
||||
|
||||
static inline void
|
||||
titan_enable_irq(unsigned int irq)
|
||||
titan_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cached_irq_mask |= 1UL << (irq - 16);
|
||||
titan_update_irq_hw(titan_cached_irq_mask);
|
||||
@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static inline void
|
||||
titan_disable_irq(unsigned int irq)
|
||||
titan_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cached_irq_mask &= ~(1UL << (irq - 16));
|
||||
titan_update_irq_hw(titan_cached_irq_mask);
|
||||
@ -144,7 +146,8 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
||||
}
|
||||
|
||||
static int
|
||||
titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
|
||||
titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
|
||||
bool force)
|
||||
{
|
||||
spin_lock(&titan_irq_lock);
|
||||
titan_cpu_set_irq_affinity(irq - 16, *affinity);
|
||||
@ -175,17 +178,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
|
||||
{
|
||||
long i;
|
||||
for (i = imin; i <= imax; ++i) {
|
||||
irq_to_desc(i)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i, ops, handle_level_irq);
|
||||
irq_set_status_flags(i, IRQ_LEVEL);
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip titan_irq_type = {
|
||||
.name = "TITAN",
|
||||
.unmask = titan_enable_irq,
|
||||
.mask = titan_disable_irq,
|
||||
.mask_ack = titan_disable_irq,
|
||||
.set_affinity = titan_set_irq_affinity,
|
||||
.name = "TITAN",
|
||||
.irq_unmask = titan_enable_irq,
|
||||
.irq_mask = titan_disable_irq,
|
||||
.irq_mask_ack = titan_disable_irq,
|
||||
.irq_set_affinity = titan_set_irq_affinity,
|
||||
};
|
||||
|
||||
static irqreturn_t
|
||||
|
@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
|
||||
}
|
||||
|
||||
static void
|
||||
wildfire_enable_irq(unsigned int irq)
|
||||
wildfire_enable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_enable_irq(irq);
|
||||
i8259a_enable_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
set_bit(irq, &cached_irq_mask);
|
||||
@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
wildfire_disable_irq(unsigned int irq)
|
||||
wildfire_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_disable_irq(irq);
|
||||
i8259a_disable_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
clear_bit(irq, &cached_irq_mask);
|
||||
@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
|
||||
}
|
||||
|
||||
static void
|
||||
wildfire_mask_and_ack_irq(unsigned int irq)
|
||||
wildfire_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
if (irq < 16)
|
||||
i8259a_mask_and_ack_irq(irq);
|
||||
i8259a_mask_and_ack_irq(d);
|
||||
|
||||
spin_lock(&wildfire_irq_lock);
|
||||
clear_bit(irq, &cached_irq_mask);
|
||||
@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
|
||||
|
||||
static struct irq_chip wildfire_irq_type = {
|
||||
.name = "WILDFIRE",
|
||||
.unmask = wildfire_enable_irq,
|
||||
.mask = wildfire_disable_irq,
|
||||
.mask_ack = wildfire_mask_and_ack_irq,
|
||||
.irq_unmask = wildfire_enable_irq,
|
||||
.irq_mask = wildfire_disable_irq,
|
||||
.irq_mask_ack = wildfire_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void __init
|
||||
@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
|
||||
for (i = 0; i < 16; ++i) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
|
||||
for (i = 40; i < 64; ++i) {
|
||||
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
|
||||
handle_level_irq);
|
||||
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
|
||||
}
|
||||
|
||||
setup_irq(32+irq_bias, &isa_enable);
|
||||
setup_irq(32+irq_bias, &isa_enable);
|
||||
}
|
||||
|
||||
static void __init
|
||||
|
@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
|
||||
visible impact on the overall performance or power consumption of the
|
||||
processor.
|
||||
|
||||
config ARM_ERRATA_751472
|
||||
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
|
||||
depends on CPU_V7 && SMP
|
||||
help
|
||||
This option enables the workaround for the 751472 Cortex-A9 (prior
|
||||
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
|
||||
completion of a following broadcasted operation if the second
|
||||
operation is received by a CPU before the ICIALLUIS has completed,
|
||||
potentially leading to corrupted entries in the cache or TLB.
|
||||
|
||||
config ARM_ERRATA_753970
|
||||
bool "ARM errata: cache sync operation may be faulty"
|
||||
depends on CACHE_PL310
|
||||
help
|
||||
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
|
||||
|
||||
Under some condition the effect of cache sync operation on
|
||||
the store buffer still remains when the operation completes.
|
||||
This means that the store buffer is always asked to drain and
|
||||
this prevents it from merging any further writes. The workaround
|
||||
is to replace the normal offset of cache sync operation (0x730)
|
||||
by another offset targeting an unmapped PL310 register 0x740.
|
||||
This has the same effect as the cache sync operation: store buffer
|
||||
drain and waiting for all buffers empty.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
@ -1391,7 +1416,7 @@ config AEABI
|
||||
|
||||
config OABI_COMPAT
|
||||
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
|
||||
depends on AEABI && EXPERIMENTAL
|
||||
depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
|
||||
default y
|
||||
help
|
||||
This option preserves the old syscall interface along with the
|
||||
|
@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
|
||||
LDFLAGS_vmlinux += --be8
|
||||
endif
|
||||
|
||||
OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
|
||||
OBJCOPYFLAGS :=-O binary -R .comment -S
|
||||
GZFLAGS :=-9
|
||||
#KBUILD_CFLAGS +=-pipe
|
||||
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
|
||||
|
6
arch/arm/boot/compressed/.gitignore
vendored
6
arch/arm/boot/compressed/.gitignore
vendored
@ -1,3 +1,7 @@
|
||||
font.c
|
||||
piggy.gz
|
||||
lib1funcs.S
|
||||
piggy.gzip
|
||||
piggy.lzo
|
||||
piggy.lzma
|
||||
vmlinux
|
||||
vmlinux.lds
|
||||
|
@ -6,6 +6,8 @@ config ARM_VIC
|
||||
|
||||
config ARM_VIC_NR
|
||||
int
|
||||
default 4 if ARCH_S5PV210
|
||||
default 3 if ARCH_S5P6442 || ARCH_S5PC100
|
||||
default 2
|
||||
depends on ARM_VIC
|
||||
help
|
||||
|
@ -36,6 +36,7 @@
|
||||
#define L2X0_RAW_INTR_STAT 0x21C
|
||||
#define L2X0_INTR_CLEAR 0x220
|
||||
#define L2X0_CACHE_SYNC 0x730
|
||||
#define L2X0_DUMMY_REG 0x740
|
||||
#define L2X0_INV_LINE_PA 0x770
|
||||
#define L2X0_INV_WAY 0x77C
|
||||
#define L2X0_CLEAN_LINE_PA 0x7B0
|
||||
|
@ -58,6 +58,9 @@
|
||||
|
||||
static inline void sysctl_soft_reset(void __iomem *base)
|
||||
{
|
||||
/* switch to slow mode */
|
||||
writel(0x2, base + SCCTRL);
|
||||
|
||||
/* writing any value to SCSYSSTAT reg will reset system */
|
||||
writel(0, base + SCSYSSTAT);
|
||||
}
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user